S9S12GN48F0VLF Freescale Semiconductor, S9S12GN48F0VLF Datasheet - Page 647

• Manufacturer Part Number: S9S12GN48F0VLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Read: Anytime
Write: Anytime
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
Freescale Semiconductor
Module Base + 0x00006
PCLKAB7
PCLKAB6
PCLKAB5
PCLKAB4
PCLKAB3
PCLKAB2
PCLKAB1
PCLKAB0
Reset
Field
unavailable bits return a zero
7
6
5
4
3
2
1
0
W
R
PCLKAB7
Pulse Width Channel 7 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 7, as shown in
1 Clock A or SA is the clock source for PWM channel 7, as shown in
Pulse Width Channel 6 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 6, as shown in
1 Clock A or SA is the clock source for PWM channel 6, as shown in
Pulse Width Channel 5 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 5, as shown in
1 Clock B or SB is the clock source for PWM channel 5, as shown in
Pulse Width Channel 4 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 4, as shown in
1 Clock B or SB is the clock source for PWM channel 4, as shown in
Pulse Width Channel 3 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 3, as shown in
1 Clock A or SA is the clock source for PWM channel 3, as shown in
Pulse Width Channel 2 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 2, as shown in
1 Clock A or SA is the clock source for PWM channel 2, as shown in
Pulse Width Channel 1 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 1, as shown in
1 Clock B or SB is the clock source for PWM channel 1, as shown in
Pulse Width Channel 0 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 0, as shown in
1 Clock B or SB is the clock source for PWM channel 0, as shown in
0
7
Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock
select is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
PCLKAB6
Figure 19-9. PWM Clock Select Register (PWMCLKAB)
0
6
Table 19-11. PWMCLK Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
PCLKAB5
0
5
PCLKAB4
NOTE
0
4
Description
PCLKAB3
0
3
PCLKAB2
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Pulse-Width Modulator (S12PWM8B8CV2)
0
2
19-6.
19-6.
19-6.
19-6.
19-5.
19-5.
19-5.
19-5.
19-6.
19-6.
19-6.
19-6.
19-5.
19-5.
19-5.
19-5.
PCLKAB1
0
1
PCLKAB0
0
0
649