S9S12GN48F0VLF Freescale Semiconductor, S9S12GN48F0VLF Datasheet - Page 716

• Manufacturer Part Number: S9S12GN48F0VLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Serial Peripheral Interface (S12SPIV5)
The main element of the SPI system is the SPI data register. The n-bit
n-bit
register. When a data transfer operation is performed, this 2n-bit
by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data read from the master SPI data
register after a transfer operation is the input data from the slave.
A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.
When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This
data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes.
A common SPI data register address is shared for reading data from the read data buffer and for writing
data to the transmit data register.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1
(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply
selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally
different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see
Section 21.4.3, “Transmission
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1
is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
21.4.1
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate
transmissions. A transmission begins by writing to the master SPI data register. If the shift register is
empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the
control of the serial clock.
1. n depends on the selected transfer width, please refer to
718
•
•
•
1
data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit
Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and
SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and
determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK
pin, the baud rate generator of the master controls the shift register of the slave peripheral.
MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin
(MISO) is determined by the SPC0 and BIDIROE control bits.
SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output
becomes low during each transmission and is high when the SPI is in idle state.
Master Mode
A change of CPOL or MSTR bit while there is a received byte pending in
the receive shift register will destroy the received byte and must be avoided.
Formats”).
MC9S12G Family Reference Manual,
NOTE
Section 21.3.2.2, “SPI Control Register 2 (SPICR2)
1
register is serially shifted n
Rev.1.23
1
data register in the master and the
Freescale Semiconductor
1
bit positions
1