LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 33

• Manufacturer Part Number: LPC1778FBD144,551
• Description: ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
• Manufacturer: NXP Semiconductors

Specifications of LPC1778FBD144,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC178x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Interface Type: CAN, I2C, I2S, SSP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• On-chip Dac: Yes
• Program Memory Type: Flash
• Factory Pack Quantity: 60
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

NXP Semiconductors
Table 3.
Not all functions are available on all parts. See
pins).
LPC178X_7X
Product data sheet
Symbol
P5[3]
P5[4]
JTAG_TDO
(SWO)
JTAG_TDI
JTAG_TMS
(SWDIO)
JTAG_TRST
JTAG_TCK
(SWDCLK)
RESET
RSTOUT
RTC_ALARM
RTCX1
RTCX2
USB_D2
VBAT
Pin description
141 G14 G10 98
206 C3
2
4
6
8
10
35
29
37
34
36
52
38
D3
C2
E3
D1
E2
M2
K3
N1
K2
L2
U1
M3
…continued
H5
K1
C4
B1
C3
C2
D4
D2
J1
H2
J2
J3
N2
143
1
3
4
5
7
24
20
26
23
25
37
27
[11]
[3]
[3]
[3]
[3]
[3]
[3]
[12]
[3]
[13]
[14]
[15]
[14]
[15]
[9]
All information provided in this document is subject to legal disclaimers.
I
I;
PU
O
I;
PU
I;
PU
I;
PU
i
I;
PU
OH
OL
-
-
-
-
Table 2
Rev. 4.1 — 15 November 2012
I/O
-
-
-
I
I/O
I/O
O
-
O
O
O
I
I
I
I
I
O
O
I
O
I/O
I
(Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and
Description
P5[3] — General purpose digital input/output pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
U4_RXD — Receiver input for USART4.
I2C0_SCL — I
specialized I
P5[4] — General purpose digital input/output pin.
U0_OE — RS-485/EIA-485 output enable signal for UART0.
R — Function reserved.
T3_MAT3 — Match output for Timer 3, channel 3.
U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
Test Data Out for JTAG interface. Also used as Serial wire trace
output.
Test Data In for JTAG interface.
Test Mode Select for JTAG interface. Also used as Serial wire
debug data input/output.
Test Reset for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than
1/6 of the CPU clock (CCLK) for the JTAG interface to operate.
Also used as serial wire clock.
External reset input. A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states,
and processor execution to begin at address 0. This pin includes
a 20 ns input glitch filter.
Reset status output. A LOW output on this pin indicates that the
device is in the reset state for any reason. This reflects the
RESET input pin and all internal reset sources.
RTC controlled output. This pin has a low drive strength and is
powered by VBAT. It is driven HIGH when an RTC alarm is
generated.
Input to the RTC 32 kHz ultra-low power oscillator circuit.
Output from the RTC 32 kHz ultra-low power oscillator circuit.
USB port 2 bidirectional D line.
RTC power supply: 3.0 V on this pin supplies power to the RTC.
2
C pad that supports I
2
C0 clock input/output (this pin uses a
32-bit ARM Cortex-M3 microcontroller
2
C Fast Mode Plus.
LPC178x/7x
© NXP B.V. 2012. All rights reserved.
Table 7
33 of 120
(EMC