LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 47

• Manufacturer Part Number: LPC1778FBD144,551
• Description: ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
• Manufacturer: NXP Semiconductors

Specifications of LPC1778FBD144,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC178x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Interface Type: CAN, I2C, I2S, SSP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• On-chip Dac: Yes
• Program Memory Type: Flash
• Factory Pack Quantity: 60
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

NXP Semiconductors
LPC178X_7X
Product data sheet
7.12.1 Features
7.11.1 Features
7.12 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
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Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Supports 8, 16, and 32-bit wide transactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x
– CRC-16: x
– CRC-32: x
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU PIO or DMA back-to-back transfer.
All information provided in this document is subject to legal disclaimers.
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