STM32F051C8T7TR STMicroelectronics, STM32F051C8T7TR Datasheet - Page 12

• Manufacturer Part Number: STM32F051C8T7TR
• Description: ARM Microcontrollers - MCU Entry-level ARM Cortex-M0 MCU 64Kb
• Manufacturer: STMicroelectronics

Specifications of STM32F051C8T7TR

• Rohs: yes

Functional overview
3
3.1
3.2
3.3
12/105
Functional overview
ARM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F051x family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1
Memories
The device has the following features:
●
●
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
The non-volatile memory is divided into two arrays:
–
–
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
–
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
®
shows the general block diagram of the device family.
16 to 64 Kbytes of embedded Flash memory for programs and data
Option bytes
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
Cortex
TM
-M0 core with embedded Flash and SRAM
Doc ID 022265 Rev 3
STM32F051x