STM32F051C8T7TR STMicroelectronics, STM32F051C8T7TR Datasheet - Page 87

• Manufacturer Part Number: STM32F051C8T7TR
• Description: ARM Microcontrollers - MCU Entry-level ARM Cortex-M0 MCU 64Kb
• Manufacturer: STMicroelectronics

Specifications of STM32F051C8T7TR

• Rohs: yes

Electrical characteristics
Table 66.
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Figure 26. SPI timing diagram - slave mode and CPHA = 0
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DuCy(SCK)
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
t
t
t
t
t
h(NSS)
t
su(MI)
t
v(SO)
v(MO)
h(MO)
su(SI)
h(MI)
h(SO)
h(SI)
OUT P UT
NSS input
(1)(2)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
I NPUT
(1)
(1)(3)
MISO
MOSI
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
t a(SO)
SPI characteristics (continued)
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
SPI slave input clock duty
cycle
t su(SI)
t w(SCKH)
t w(SCKL)
Parameter
t SU(NSS)
MS B O UT
t v(SO)
M SB IN
t h(SI)
t c(SCK)
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode
Doc ID 022265 Rev 3
Conditions
PCLK
BI T6 OUT
PCLK
B I T1 IN
t h(SO)
= 20 MHz
= 36 MHz,
2Tpclk + 10
Tpclk/2 -2
4Tpclk
LSB IN
t r(SCK)
t f(SCK)
11.5
LSB OUT
Min
25
4
5
4
5
0
2
-
-
0
t h(NSS)
t dis(SO)
Tpclk/2 + 1
3Tpclk
Max
22.5
18
75
6
-
-
-
-
-
-
-
-
STM32F051x
ai14134c
Unit
ns
%