M24LR64E-RDW6T/2 STMicroelectronics, M24LR64E-RDW6T/2 Datasheet

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... More than 1 million write cycles More than 40-year data retention Multiple password protection in RF mode Single password protection in I Package – ECOPACK2 Halogen-free) Doc ID 022712 Rev 3 M24LR64E-R Datasheet production data SO8 (MN) 150 mils width TSSOP8 (DW mode 2 C mode ® ...

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... Antenna coil (AC0, AC1 2.5.1 2.6 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SS 2.7 Supply voltage (V 2.7.1 2.7.2 2.7.3 2.7.4 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 M24LR64E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 4.2 M24LR64E-R block security in I²C mode (I2C_Write_Lock bit area 4.3 Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 ...

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... Communication signal from VCD to M24LR64E Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 Data coding mode: 1 out 9.3 VCD to M24LR64E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . present password command description . . . . . . . . . . . . . . . . . . . . . 39 ...

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... Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.1 11.1.2 11.2 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2.1 11.2.2 12 M24LR64E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1.1 12.1.2 12.2 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.2.1 12.2.2 12.3 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.1 12.3.2 12.4 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 ...

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... Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.1 t1: M24LR64E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25 VCD new request delay when no response is received 3 from the M24LR64E Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Doc ID 022712 Rev 3 Contents 5/140 ...

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... Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 27 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 29 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 31 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6/140 Doc ID 022712 Rev 3 M24LR64E-R ...

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... M24LR64E-R Appendix A Anticollision algorithm (informative 135 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Appendix B CRC (informative 136 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Appendix C Application family identifier (AFI) (informative 138 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Doc ID 022712 Rev 3 Contents 7/140 ...

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... Response data rates Table 21. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 22. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 23. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 24. M24LR64E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 25. M24LR64E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 26. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 27. Definition of request flags Table 28. Request flags when Bit Table 29 ...

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... M24LR64E-R Table 49. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 50. Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 89 Table 51. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 52. Select Block response format when Error_flag is NOT set Table 53. Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 54. Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 55. ...

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... Table 129. TSSOP8 – 8-lead thin shrink small outline, package mechanical data 133 Table 130. Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 131. CRC definition 136 Table 132. AFI coding 138 Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10/140 Doc ID 022712 Rev 3 M24LR64E-R ...

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... End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 58 Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 47. M24LR64E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 = 400 kHz): maximum R value versus bus parasitic bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 022712 Rev 3 ...

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... List of figures Figure 48. M24LR64E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 49. M24LR64E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 73 Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 52. M24LR64E RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . 81 Figure 53. Stay Quiet frame exchange between VCD and M24LR64E Figure 54 ...

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... The M24LR64E-R is organized as 8192 × 8 bits in the I 15693 and ISO 18000-3 mode 1 RF mode. The M24LR64E-R also features an energy harvesting analog output, as well as a user- configurable digital output pin toggling during either RF write in progress or RF busy mode. Figure 1. ...

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... Outgoing data is generated by the M24LR64E-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data is transferred from the M24LR64E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s in high data rate mode. The M24LR64E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz ...

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... This configurable output signal is used either to indicate that the M24LR64E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR64E-R is powered by the Vcc pin open drain output and a pull-up resistor must be connected from RF WIP/BUSY ...

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... Supply voltage (V This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on V M24LR64E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V 2.7.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V ...

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... M24LR64E-R 2 Figure Fast mode (f capacitance (C 100 10 Here R bus × C bus = 120 Figure bus protocol SCL SDA SCL SDA Start Condition SCL SDA = 400 kHz): maximum bus 30 pF 100 1000 Bus line capacitor (pF) SDA SDA Start ...

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... Signal descriptions Table 2. Device select code Device select code 1. The most significant bit, b7, is sent first not connected to any external pin however used to address the M24LR64E-R as described in Section 3 and Section Table 3. Address most significant byte b15 b14 Table 4. Address least significant byte ...

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... M24LR64E-R 3 User memory organization The M24LR64E-R is divided into 16 sectors of 32 blocks of 32 bits, as shown in Figure 6 shows the memory sector organization. Each sector can be individually read- and/or write-protected using a specific password command. Read and write operations are possible if the addressed data is not in a protected sector. ...

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... Sector details The M24LR64E-R user memory is divided into 16 sectors. Each sector contains 1024 bits. The protection scheme is described mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector ...

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... M24LR64E-R Table 5. Sector details Sector RF block number address byte Bits [31:24] address 0 0 user 1 4 user 2 8 user 3 12 user 4 16 user 5 20 user 6 24 user 7 28 user 8 32 ...

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... Doc ID 022712 Rev 3 M24LR64E-R Bits [23:16] Bits [15:8] Bits [7:0] user user user user user user user user user user user user user user user user ... ... ... ...

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... M24LR64E-R Table 5. Sector details (continued) Sector RF block number address 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 63 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 ...

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... M24LR64E-R block security in RF mode The M24LR64E-R provides a special protection mechanism based on passwords mode, each memory sector of the M24LR64E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR64E-R is assigned with a Sector security status byte ...

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... Password control bits The M24LR64E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Password system area Add The dedicated commands for protection in RF mode are: ...

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... Present-sector password: The Present-sector password command is used to present one of the three passwords to the M24LR64E-R in order to modify the access rights of all the memory sectors linked to that password password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued ...

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... To access the I2C_Write_Lock bit area, the device select code used for any I must have the E2 Chip Enable address at 1. Using these 16 bits possible to write-protect all the 16 sectors of the M24LR64E-R memory. Each bit controls the I is always possible to unprotect a sector in the I reset to 0, the corresponding sector is unprotected ...

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... When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode. The purpose of this mode is to indicate to the I²C bus master whether the M24LR64E-R is busy in RF mode or not. In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution ...

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... M24LR64E-R Vout sink current configuration The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the Configuration byte (see The minimum power level required on AC0-AC1 RF input P voltage Vout, as well as the maximum current consumption I corresponding to the <EH_cfg1,EH_cfg0> bit values are described in Table 14. ...

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... FIELD_ON indicator bit The FIELD_ON indicator bit located as bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR64E-R is sufficient to execute RF commands. When FIELD_ON = 0, the M24LR64E-R is not able to execute any RF commands. When FIELD_ON =1, the M24LR64E-R is able to execute any RF commands. ...

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... M24LR64E-R power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection necessary to use the I password described in all the presented bits correspond to the stored ones — also possible to modify the I password using the I The next three 32-bit blocks store the three RF passwords ...

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... The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The M24LR64E-R device is a slave in all communications. ...

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... M24LR64E-R 5.5.1 I²C timeout on Start condition I²C communication with the M24LR64E-R starts with a valid Start condition, followed by a device select code. If the delay between the Start condition and the following rising edge of the Serial Clock (SCL) that samples the most significant of the Device Select exceeds the t ...

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... Byte address Byte address R/W ACK ACK Dev select Byte address Byte address R/W NO ACK NO ACK Data in N Doc ID 022712 Rev 3 M24LR64E-R Initial sequence ACK NO ACK Data in ACK NO ACK Data in 1 Data in 2 AI15115 Figure 8, and waits for two (Table 4). Bits b15 to b0 form ...

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... M24LR64E-R When the bus master generates a Stop condition immediately after the Ack bit (in the tenth- bit time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. A Stop condition at any other time slot does not trigger the internal write cycle. ...

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... NO Data for the Write operation Continue the Write operation , but the typical time is shorter. To make use of this, a polling sequence Figure 10, is: Doc ID 022712 Rev 3 M24LR64E-R Send address and receive ACK Start YES condition Device select with Continue the Random Read operation ...

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... M24LR64E-R Figure 11. Read mode sequences Current Address Read Random Address Read Sequential Current Read Sequential Random Read 1. The seven most significant bits of the device select code of a random read (in the first and fourth bytes) must be identical. ACK NO ACK Dev select Data out ...

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... For all Read commands, the device waits, after each byte read, for an acknowledgment during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 38/140 Figure 11. Doc ID 022712 Rev 3 M24LR64E-R ...

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... It is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64E-R does not start the internal comparison. When the bus master generates a Stop condition immediately after the Ack bit (during the tenth bit time slot), an internal delay equivalent to the write cycle time is triggered ...

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... I C write password command description 2 The I C write password command is used to write a 32-bit block into the M24LR64E-R I password system area. This command is used in I value. It cannot be used to update any of the RF passwords. After the write cycle, the new password value is automatically activated. The I ...

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... The DSFID is programmed to FFh and the AFI is programmed to 00h. Configuration byte set to F4h: Bit 7 to bit 4: all set to 1 Bit 3: set to 0 (RF BUSY mode on RF WIP/BUSY pin) Bit 2: set to 1 (Energy harvesting not activated by default) Bit 1 and bit 0: set to 0 M24LR64E-R memory initial state Doc ID 022712 Rev 3 41/140 ...

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... RF device operation 7 RF device operation The M24LR64E-R is divided into 16 sectors of 32 blocks of 32 bits, as shown in Each sector can be individually read- and/or write-protected using a specific lock or password command. Read and Write operations are possible if the addressed block is not protected. During a Write, the 32 bits of the block are replaced by the new 32-bit value. ...

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... Commands The M24LR64E-R supports the following commands: Inventory, used to perform the anticollision sequence. Stay quiet, used to put the M24LR64E-R in quiet mode, where it does not respond to any inventory command. Select, used to select the M24LR64E-R. After this command, the M24LR64E-R processes all Read/Write commands with Select_flag set. ...

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... Power transfer Power is transferred to the M24LR64E-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR64E-R and the VCD. The RF operating field of the VCD is transformed on the M24LR64E-R antenna voltage which is rectified, filtered and internally regulated. During communications, the amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator ...

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... Depending on the choice made by the VCD, a “pause” is created as described in and Figure 15. The M24LR64E-R is operational for the 100% modulation index or for any degree of modulation index between 10% and 30% (see Figure 14. 100% modulation waveform Carrier Amplitude ...

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... Communication signal from VCD to M24LR64E-R Table 19. 10% modulation parameters Symbol hr hf Figure 15. 10% modulation waveform Carrier Carrier Amplitude Amplitude Modulation Modulation Modulation Index Index Index The VICC shall be operational for any value of modulation index between 10 % and 30 %. ...

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... Data rate and data coding The data coding implemented in the M24LR64E-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR64E-R. The selection is made by the VCD and indicated to the M24LR64E-R within the start of frame (SOF). 9.1 Data coding mode: 1 out of 256 The value of one single byte is represented by the position of one pause ...

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... Figure 19 48/140 . . . . . Figure 18 illustrates the 1 out of 4 pulse position technique and shows the transmission of E1h (225d - 1110 0001b) by the VCD. Doc ID 022712 Rev 3 M24LR64E-R 9.44 µs 18.88 µ Time Period one of 256 AI06657 ) determines the value of the two bits. ...

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... M24LR64E-R Figure 18. 1 out of 4 coding mode Pulse position for "00" 9.44 µs 9.44 µs Pulse position for "01" (1=LSB) Pulse position for "10" (0=LSB) Pulse position for "11" Figure 19. 1 out of 4 coding example 10 75.52µs 75.52 µs 28.32 µs 9.44 µs 75.52 µ ...

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... Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are implemented using code violation. Unused options are reserved for future use. The M24LR64E-R is ready to receive a new command frame from the VCD 311.5 µs (t after sending a response frame to the VCD. ...

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... M24LR64E-R Figure 22. EOF for either data coding mode 9.44µs 9.44µs 37.76µs Doc ID 022712 Rev 3 Data rate and data coding AI06662 51/140 ...

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... Data rates The M24LR64E-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. For fast commands, the selected data rate is multiplied by two. ...

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... M24LR64E-R 11 Bit representation and coding Data bits are encoded using Manchester coding, according to the following schemes. For the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4 and all times increase by this factor. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2 ...

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... For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by 16 pulses at 423.75 kHz (f Figure 30. Logic 1, low data rate, fast commands 54/140 /32) followed by an unmodulated time of C Figure 27. 151.04µs Figure 75.52µs Figure 29. 151.04µs /32), as shown in Figure C 75.52µs Doc ID 022712 Rev 3 M24LR64E-R ai12068 /32) followed 28. ai12069 ai12070 30. ai12071 ...

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... M24LR64E-R 11.2 Bit coding using two subcarriers 11.2.1 High data rate A logic 0 starts with eight pulses at 423.75 kHz (f 484.28 kHz (f /28), as shown in C for the Fast commands. Figure 31. Logic 0, high data rate A logic 1 starts with nine pulses at 484.28 kHz (f 423.75 kHz (f /32), as shown in C for the Fast commands ...

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... M24LR64E-R to VCD frames 12 M24LR64E-R to VCD frames Frames are delimited by an SOF and an EOF. They are implemented using code violation. Unused options are reserved for future use. For the low data rate, the same subcarrier frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4. ...

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... C Figure 226.56µs /28), followed by 24 pulses at 423.75 kHz C Figure 39. 112.39µs 37.46µs /28), followed by 96 pulses at 423.75 kHz C Figure 40. 449.56µs Doc ID 022712 Rev 3 M24LR64E-R to VCD frames 38. 75.52µs ai12081 ai12082 149.84µs ai12083 57/140 ...

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... M24LR64E-R to VCD frames 12.3 EOF when using one subcarrier 12.3.1 High data rate The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and an unmodulated time of 18.88 µs, followed by 24 pulses at 423.75 kHz (f of 56.64 µs, as shown in Figure 41. End of frame, high data rate, one subcarrier 37.76µ ...

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... Bit coding using two subcarriers is not supported for the Fast commands. Figure 46. End of frame, low data rate, two subcarriers 149.84µs Figure 45. 37.46µs 112.39µs Figure 46. Doc ID 022712 Rev 3 M24LR64E-R to VCD frames /32) and 27 pulses at 484.28 kHz C ai12088 /32) and 108 pulses at 484.28 kHz C 449.56µs ai12089 59/140 ...

Page 60

... Unique identifier (UID) 13 Unique identifier (UID) The M24LR64E-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises: eight MSBs with a value of E0h, the IC manufacturer code “ST 02h” bits (ISO/IEC 7816-6/AM1), a unique serial number on 48 bits ...

Page 61

... M24LR64E-Rs present, only those that meet the required application criteria. Figure 47. M24LR64E-R decision tree for AFI The AFI is programmed by the M24LR64E-R issuer (or purchaser) in the AFI register. Once programmed and locked, it can no longer be modified. The most significant nibble of the AFI is used to code one specific or all application families. ...

Page 62

... EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field. Upon reception of a request from the VCD, the M24LR64E-R verifies that the CRC value is valid invalid, the M24LR64E-R discards the frame and does not answer the VCD. Upon reception of a response from the M24LR64E- recommended that the VCD verifies whether the CRC value is valid ...

Page 63

... VCD and the M24LR64E-R in both directions based on the concept of “VCD talks first”. This means that an M24LR64E-R does not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of: a request from the VCD to the M24LR64E-R, a response from the M24LR64E-R to the VCD ...

Page 64

... M24LR64E-R protocol description Figure 48. M24LR64E-R protocol timing Request VCD (Table M24LR64 E-R Timing 64/140 frame 23) Response frame (Table 24) <-t -> <-t 1 Doc ID 022712 Rev 3 M24LR64E-R Request frame (Table 23) Response frame (Table -> <-t -> 24) <-t -> 2 ...

Page 65

... Quiet Selected Transitions between these states are specified in 17.1 Power-off state The M24LR64E the Power-off state when it does not receive enough energy from the VCD. 17.2 Ready state The M24LR64E the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR64E-R answers any request where the Select_flag is not set ...

Page 66

... Address_Flag is set AND where Inventory_Flag is not set 1. The M24LR64E-R returns to the Power Off state if the tag is out of the RF field for at least t refer to application note AN4125 for more information. 2. The intention of the state transition method is that only one M24LR64E-R should be in the Selected state at a time ...

Page 67

... Select_flag set to 1 executes it and returns a response to the VCD as specified in the command description. Only M24LR64E-Rs in the Selected state answer a request where the Select_flag is set to 1. The system design ensures in theory that only one M24LR64E-R can be in the Select state at a time. Doc ID 022712 Rev 3 Modes ...

Page 68

... F 19.1 Request flags In a request, the “flags” field specifies the actions to be performed by the M24LR64E-R and whether corresponding fields are present or not. The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits define the M24LR64E-R selection criteria ...

Page 69

... The request is not addressed. UID field is not present. The 0 request is executed by all M24LR64E-Rs. (1) The request is addressed. UID field is present. The request is 1 executed only by the M24LR64E-R whose UID matches the UID specified in the request. 0 Option not activated. 1 Option activated. 0 Level ...

Page 70

... General response format S O Response_flags F 20.1 Response flags In a response, the flags indicate how actions have been performed by the M24LR64E-R and whether corresponding fields are present or not. The response flags consist of eight bits. Table 31. Definitions of response flags Bit Nb Bit 1 Error_flag Bit 2 ...

Page 71

... M24LR64E-R 20.2 Response error code If the Error_flag is set by the M24LR64E-R in the response, the Error code field is present and provides information about the error that occurred. Error codes not specified in Table 32. Response error code definition Error code 03h 0Fh 10h 11h 12h 13h ...

Page 72

... The purpose of the anticollision sequence is to inventory the M24LR64E-Rs present in the VCD field using their unique ID (UID). The VCD is the master of communications with one or several M24LR64E-Rs. It initiates an M24LR64E-R communication by issuing the Inventory request. The M24LR64E-R sends its response in the determined slot or does not respond. ...

Page 73

... The first slot starts immediately after the request EOF is received. To switch to the next slot, the VCD sends an EOF. The following rules and restrictions apply M24LR64E-R answer is detected, the VCD may switch to the next slot by sending an EOF. If one or more M24LR64E-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot ...

Page 74

... Request processing by the M24LR64E-R 22 Request processing by the M24LR64E-R Upon reception of a valid request, the M24LR64E-R performs the following algorithm: NbS is the total number of slots ( the current slot number (0 to 15) LSB (value, n) function returns the n Less Significant Bits of value MSB (value, n) function returns the n Most Significant Bits of value “ ...

Page 75

... The VCD sends an Inventory request frame terminated by an EOF. The number of slots is 16. M24LR64E-R_1 transmits its response in Slot the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD. The VCD sends an EOF in order to switch to the next slot. ...

Page 76

Slot 0 Inventory VCD SOF EOF EOF Request Response M24RF64s Response Response 1 Timing Comment Collision collision Time Slot 1 Slot 2 Slot 3 Request to EOF EOF SOF M24RF64_1 Response 2 4 Response 3 5 ...

Page 77

... M24LR64E-R 24 Inventory Initiated command The M24LR64E-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader possible to miss tags using the standard inventory command ...

Page 78

... EOF from the M24LR64E-Rs. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR64E- also the time after which the VCD may send a new request to the M24LR64E- described in Figure ...

Page 79

... M24LR64E-R 26 Command codes The M24LR64E-R supports the commands described in this section. Their codes are given in Table 36. Table 36. Command codes Command code standard 01h 02h 20h 21h 23h 25h 26h 27h 28h 29h 2Ah 2Bh Function Inventory Stay Quiet Read Single Block ...

Page 80

... Inventory response format Response Response_ SOF flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR64E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value min = 4384/f ...

Page 81

... M24LR64E replies in slot n. RF_Busy is released after M24LR64E response command F RF_Busy 2) Slot n never occurs. RF_Busy is only released by Power-off RF_Busy 3) VCD sends a Valid command before slot n. RF_Busy is released after M24LR64E response RF_Busy 4) VCD sends a Bad command before slot n. RF_Busy is released after VCD command ...

Page 82

... Command codes 26.2 Stay Quiet Command code = 0x02 On receiving the Stay Quiet command, the M24LR64E-R enters the Quiet state if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. When in the Quiet state: the M24LR64E-R does not process any request if the Inventory_flag is set, the M24LR64E-R processes any Addressed request ...

Page 83

... On receiving the Read Single Block command, the M24LR64E-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag is supported. ...

Page 84

... The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag is supported. During the RF write cycle W otherwise the M24LR64E-R may not program correctly the data into the memory. The W time is equal to t 1nom Table 44. ...

Page 85

... M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write Single Block command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid write single block command to the beginning of the M24LR64E-R response) ...

Page 86

... Command codes Figure 56. M24LR64E RF-Busy management following Write command 1) M24LR64E replies. RF_Busy is released after M24LR64E response command F RF_Busy 2) M24LR64E replies when option flag is set. RF_Busy is released after M24LR64E response command F RF_Busy 3) VCD sends a forbidden Write (sector lock, password-protected). RF_Busy is released after M24LR64E command ...

Page 87

... Write & verify sequence, as shown in Figure 57. M24LR64E RF-Wip management following Write command 1) M24LR64E replies. RF_Wip is released after M24LR64E response command F RF_Wip 2) M24LR64E replies when option flag is set. RF_Wip is released after M24LR64E response command F RF_Wip 3) VCD sends a forbidden Write (sector lock, password-protected). RF_Wip is released after M24LR64E command ...

Page 88

... The maximum number of blocks is fixed at 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR64E-R returns an error code. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code ...

Page 89

... If the UID does not match its own UID, the selected M24LR64E-R returns to the Ready state and does not send a response. The M24LR64E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated error occurs, the M24LR64E-R remains in its current state. ...

Page 90

... When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 26.7 Reset to Ready On receiving a Reset to Ready command, the M24LR64E-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR64E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. Table 54. ...

Page 91

... Write AFI On receiving the Write AFI request, the M24LR64E-R programs the 8-bit AFI value to its memory. The Option_flag is supported. During the RF write cycle W otherwise the M24LR64E-R may not write correctly the AFI value into the memory. The W time is equal to t 1nom 8 bits ...

Page 92

... Response parameter: Error code as Error_flag is set – 12h: the specified block is locked and its contents cannot be changed – 13h: the specified block was not successfully programmed Figure 61. Write AFI frame exchange between VCD and M24LR64E-R VCD M24LR64E-R M24LR64E-R 92/140 Write (1) ...

Page 93

... Write AFI command to the beginning of the M24LR64E-R response). 26.9 Lock AFI On receiving the Lock AFI request, the M24LR64E-R locks the AFI value permanently. The Option_flag is supported. During the RF write cycle W otherwise the M24LR64E-R may not lock correctly the AFI value in memory. The W equal × ...

Page 94

... M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock AFI command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of valid Lock AFI command to the beginning of the M24LR64E-R response) ...

Page 95

... Write DSFID On receiving the Write DSFID request, the M24LR64E-R programs the 8-bit DSFID value to its memory. The Option_flag is supported. During the RF write cycle W otherwise the M24LR64E-R may not write correctly the DSFID value in memory. The W time is equal to t 1nom Table 63. ...

Page 96

... Lock DSFID On receiving the Lock DSFID request, the M24LR64E-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle W otherwise the M24LR64E-R may not lock correctly the DSFID value in memory. The W is equal × 302 µs. 1nom Table 66. ...

Page 97

... M24LR64E-R response). 26.12 Get System Info When receiving the Get System Info command, the M24LR64E-R sends back its information data in the response. The Option_flag is not supported. The Get System Info can be issued in both Addressed and Non Addressed modes. The Protocol_extension_flag can be set ...

Page 98

... Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are present. UID code on 64 bits DSFID value AFI value Memory size. The M24LR64E-R provides 2048 blocks (07FFh bytes (03h) IC reference: the 8 bits are significant. Table 72. Get System Info response format when Error_flag is set Response ...

Page 99

... For example, a value of '06' in the “Number of blocks” field requests to return the security status of seven blocks. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. ...

Page 100

... VCD M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get Multiple Block Security Status command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. ...

Page 101

... On receiving the Write-sector Password command, the M24LR64E-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. The Option_flag is supported. During the RF write cycle time, W 10%), otherwise the M24LR64E-R may not correctly program the data into the memory. The W time is equal selected password is automatically activated ...

Page 102

... Care must be taken when issuing the Lock- sector command as all the blocks belonging to the same sector are automatically locked by a single command. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. During the RF write cycle W otherwise the M24LR64E-R may not correctly lock the memory block ...

Page 103

... Figure 68. Lock-sector frame exchange between VCD and M24LR64E-R VCD M24LR64E-R M24LR64E-R Table 81) ...

Page 104

... The Option_flag is supported. During the comparison cycle equal to W 10%), otherwise the M24LR64E-R Password value may not be correctly compared. The W time is equal to t 1nom ...

Page 105

... The Option_flag is supported. The data rate of the response is multiplied by 2. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code ...

Page 106

... Fast Read Single Block response format when Error_flag is set Response Response_flags SOF Response parameter: Error code as Error_flag is set: – 10h: the specified block is not available – 15h: the specified block is read-protected Figure 70. Fast Read Single Block frame exchange between VCD and M24LR64E-R VCD M24LR64E-R 106/140 Sector security (1) status 8 bits b ...

Page 107

... Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64E-R does not answer the Fast Inventory Initiated command. The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code. On receiving the Fast Inventory Initiated request, the M24LR64E-R runs the anticollision sequence ...

Page 108

... Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR64E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR64E-R. The data rate of the response is multiplied by 2. The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code ...

Page 109

... If the number of blocks overlaps sectors, the M24LR64E-R returns an error code. The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. ...

Page 110

... VCD M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Fast Read Multiple Block command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 110/140 ...

Page 111

... Inventory Initiated Before receiving the Inventory Initiated command, the M24LR64E-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64E-R does not answer the Inventory Initiated command. On receiving the Inventory Initiated request, the M24LR64E-R runs the anticollision sequence ...

Page 112

... Command codes When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF starting the inventory command to the end of the M24LR64E-R response. If the M24LR64E- R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 until the next RF power-off. ...

Page 113

... On receiving the ReadCfg command, the M24LR64E-R reads the Configuration byte and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 114

... On receiving the WriteEHCfg command, the M24LR64E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag is supported, the Inventory_flag is not supported. ...

Page 115

... On receiving the WriteDOCfg command, the M24LR64E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. ...

Page 116

... M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the WriteEHCfg command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to the beginning of the M24LR64E-R response) ...

Page 117

... M24LR64E-R 26.26 SetRstEHEn On receiving the SetRstEHEn command, the M24LR64E-R sets or resets the EH_enable bit in the volatile Control register. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag and the Inventory_flag are not supported. ...

Page 118

... On receiving the CheckEHEn command, the M24LR64E-R reads the Control register and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag the M24LR64E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 119

... Figure 78. CheckEHEn frame exchange between VCD and M24LR64E-R VCD M24LR64E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the CheckEHEn command to the end of the M24LR64E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. Error code ...

Page 120

... Parameter Sawn wafer on UV tape UFDFPN8 (MLP8), SO8, TSSOP8 UFDFPN8 (MLP8), SO8, TSSOP8 VAC0-VAC1 VAC0-GND, or VAC1-GND AC0, AC1 (4) Other pads Doc ID 022712 Rev 3 M24LR64E-R Min. Max. Unit –40 85 ° °C (1) 6 months kept in its original packing form – ...

Page 121

... M24LR64E and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in I tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...

Page 122

... 2 SDA connected to V CC. Doc ID 022712 Rev 3 M24LR64E-R Min. Max ± 2 ± ± 100 kHz 400 kHz c 100 = 400 kHz c 200 = 400 kHz ...

Page 123

... M24LR64E-R 2 Table 123 characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW t START_OUT ( XH1XH2 R ( XL1XL2 DL1DL2 DXCX SU:DAT t t CLDX HD:DAT t t CLQX DH (4)( CLQV AA ( CHDX SU:STA t t DLCL HD:STA t t CHDH ...

Page 124

... SDA In tCHDH Stop condition SCL tCLQV SDA Out 124/140 tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle tCHCL tCLQX Data valid Data valid Doc ID 022712 Rev 3 M24LR64E-R tXL1XL2 tCHDH tDHDL Stop Start condition condition tCHDX Start condition tDL1DL2 AI00795e ...

Page 125

... RFSBL Minimum time from carrier t MIN CD generation to first data f Subcarrier frequency high SH f Subcarrier frequency low SL t Time for M24LR64E-R response 1 t Time between commands 2 RF write time (including internal W t Verify) I Operating current (Read) CC_RF C ...

Page 126

... Symbol T Ambient operating temperature A Figure 81 shows an ASK modulated signal from the VCD to the M24LR64E-R. The test conditions for the AC/DC parameters are: Close coupling condition with tester antenna (1 mm) M24LR64E-R performance measured at the tag antenna M24LR64E-R synchronous timing, transmit and receive 126/140 ...

Page 127

... M24LR64E-R Figure 81. ASK modulated signal Table 126 below summarizes respectively the minimum AC0-AC1 input power level P required for the Energy harvesting mode, the corresponding maximum current AC1_min consumption I sink_max harvesting fan-out configurations defined by bits b0 and b1 of the Configuration byte. Table 126. Energy harvesting ...

Page 128

... RF electrical parameters Figure 82. Energy harvesting: V Figure 83. Energy harvesting: working domain range 11 Fan out ( 0.3 mA 128/140 min vs. I out sink 1 A/m 1.6 A/m 2.4 A/m Doc ID 022712 Rev 3 M24LR64E-R MS19777V1 Working domain when Range 11 is selected Field 3.5 A/m 5 A/m (Hrms) MS19790V1 ...

Page 129

... M24LR64E-R Figure 84. Energy harvesting: working domain range 10 Fan out ( 0.3 mA Figure 85. Energy harvesting: working domain range 01 Fan out ( 0 A/m 1.6 A/m 2.4 A/m 1 A/m 1.6 A/m 2.4 A/m Doc ID 022712 Rev 3 RF electrical parameters Working domain when Range 10 is selected Field 3.5 A/m 5 A/m (Hrms) MS19791V1 ...

Page 130

... RF electrical parameters Figure 86. Energy harvesting: working domain range 00 Fan out ( 0.3 mA 130/140 1 A/m 1.6 A/m 2.4 A/m Doc ID 022712 Rev 3 M24LR64E-R Working domain when Range 00 is selected Field 3.5 A/m 5 A/m (Hrms) MS19793V1 ...

Page 131

... M24LR64E-R 30 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline 1. Drawing is not to scale. Table 127. SO8N – ...

Page 132

... Doc ID 022712 Rev 3 M24LR64E Pin must not be connected SS (1) inches Typ Min 0.0217 0.0177 0.0008 0.0000 ...

Page 133

... M24LR64E-R Figure 89. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 129. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits. ...

Page 134

... E = support for energy harvesting Operating voltage 1 Package MN = SO8N (150 mils width UFDFPN8 (MLP8 TSSOP8 Device grade 6 = industrial: device tested with standard test flow over – °C Option T = Tape and reel packing Capacitance /2 = 27.5 pF 134/140 M24LR64E-R MN Doc ID 022712 Rev 3 M24LR64E ...

Page 135

... M24LR64E-R is inventoried then store (M24LR64E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ...

Page 136

... CRC (informative) B.1 CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64E- R and from M24LR64E-R to VCD. Table 131. CRC definition CRC type ...

Page 137

... M24LR64E-R number_of_databytes = NUMBER_OF_BYTES; } else // check CRC { number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; for ( < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for ( < 8; j++) { if (current_crc_value & 0x0001) { POLYNOMIAL; } else { } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // current_crc_value is now ready to be appended to the data ...

Page 138

... Application family identifier (AFI) (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR64E-Rs present only the one meeting the required application criteria programmed by the M24LR64E-R issuer (the purchaser of the M24LR64E-R). Once locked, it cannot be modified ...

Page 139

... Section 7.1: RF communication and energy harvesting on page 42 and Figure 49: M24LR64E-R state transition diagram on page 66. 2 Updated clock pulse width values in on page 123. Updated notes for Figure 49: M24LR64E-R state transition diagram on 3 page 66. Doc ID 022712 Rev 3 Revision history Changes Table 123: I2C AC characteristics 139/140 ...

Page 140

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 140/140 Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 022712 Rev 3 M24LR64E-R ...