M24LR64E-RDW6T/2 STMicroelectronics, M24LR64E-RDW6T/2 Datasheet - Page 62

• Manufacturer Part Number: M24LR64E-RDW6T/2
• Description: EEPROM 64Kbit EEProm 400kHz 13.56Mhz 1.8 to 5.5V
• Manufacturer: STMicroelectronics

Specifications of M24LR64E-RDW6T/2

• Rohs: yes
• Memory Size: 64 Kbit
• Organization: 8192 x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 400 kHz
• Maximum Operating Current: 20 uA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 90 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Access Time: 900 ns
• Interface Type: I2C
• Minimum Operating Temperature: 0 C
• Operating Current: 20 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.8 V

Data storage format identifier (DSFID)
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Data storage format identifier (DSFID)
The data storage format identifier indicates how the data is structured in the M24LR64E-R
memory. The logical organization of data can be known instantly using the DSFID. It can be
programmed and locked using the Write DSFID and Lock DSFID commands.
CRC
The CRC used in the M24LR64E-R is calculated as per the definition in ISO/IEC 13239. The
initial register contents are all ones: “FFFF”.
The two-byte CRC is appended to each request and response, within each frame, before
the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.
Upon reception of a request from the VCD, the M24LR64E-R verifies that the CRC value is
valid. If it is invalid, the M24LR64E-R discards the frame and does not answer the VCD.
Upon reception of a response from the M24LR64E-R, it is recommended that the VCD
verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the
discretion of the VCD designer.
The CRC is transmitted least significant byte first. Each byte is transmitted least significant
bit first.
Table 22.
LSBit MSBit
CRC transmission rules
CRC 16 (8 bits)
LSByte
Doc ID 022712 Rev 3
LSBit MSBit
CRC 16 (8 bits)
MSByte
M24LR64E-R