M24LR64E-RDW6T/2 STMicroelectronics, M24LR64E-RDW6T/2 Datasheet - Page 33

• Manufacturer Part Number: M24LR64E-RDW6T/2
• Description: EEPROM 64Kbit EEProm 400kHz 13.56Mhz 1.8 to 5.5V
• Manufacturer: STMicroelectronics

Specifications of M24LR64E-RDW6T/2

• Rohs: yes
• Memory Size: 64 Kbit
• Organization: 8192 x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 400 kHz
• Maximum Operating Current: 20 uA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 90 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Access Time: 900 ns
• Interface Type: I2C
• Minimum Operating Temperature: 0 C
• Operating Current: 20 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.8 V

M24LR64E-R
5.5.1
5.5.2
5.6
I²C timeout on Start condition
I²C communication with the M24LR64E-R starts with a valid Start condition, followed by a
device select code.
If the delay between the Start condition and the following rising edge of the Serial Clock
(SCL) that samples the most significant of the Device Select exceeds the t
(see
until the next valid Start condition.
Figure 7.
I²C timeout on clock period
During data transfer on the I²C bus, if the serial clock pulse width high (
pulse width low (
block is reset and any further incoming data transfer is ignored until the next valid Start
condition.
Memory addressing
To start a communication between the bus master and the slave device, the bus master
must initiate a Start condition. Following this, the bus master sends the device select code,
shown in
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
“Address” (E2,1,1). To address the memory array, the 4-bit device type identifier is 1010b.
Refer to
The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
SCL
SDA
Table
Table
Table 2
123), the I²C logic block is reset and further incoming data transfer is ignored
I²C timeout on Start condition
condition
2.
Start
t
CLCH
(on Serial Data (SDA), the most significant bit first).
) exceeds the maximum value specified in
Doc ID 022712 Rev 3
t
START_OUT
Table
I
123, the I²C logic
2
t
C device operation
CHCL
START_OUT
) or serial clock
MS19779V1
time
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