M24LR64E-RDW6T/2 STMicroelectronics, M24LR64E-RDW6T/2 Datasheet - Page 38

• Manufacturer Part Number: M24LR64E-RDW6T/2
• Description: EEPROM 64Kbit EEProm 400kHz 13.56Mhz 1.8 to 5.5V
• Manufacturer: STMicroelectronics

Specifications of M24LR64E-RDW6T/2

• Rohs: yes
• Memory Size: 64 Kbit
• Organization: 8192 x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 400 kHz
• Maximum Operating Current: 20 uA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 90 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Access Time: 900 ns
• Interface Type: I2C
• Minimum Operating Temperature: 0 C
• Operating Current: 20 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.8 V

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2
C device operation
Read operations
Read operations are performed independently of the state of the I2C_Write_Lock bit.
After the successful completion of a read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Random Address Read
A dummy write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls over”, and the device continues to output data from memory
address 00h.
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
11) but without sending a Stop condition. Then, the bus master sends another Start
11, without acknowledging the byte.
Figure
Doc ID 022712 Rev 3
11.
M24LR64E-R