5CSEBA6U23C7N Altera Corporation, 5CSEBA6U23C7N Datasheet

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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www ...

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... FPGA General-purpose I/Os (GPIOs) Low-power high-speed serial interface Altera Corporation TSMC's 28-nm low-power (28LP) process technology 1.1 V core voltage Wirebond low-halogen packages Multiple device densities with compatible package footprints for seamless migration between different device densities RoHS-compliant options M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC) Memory logic array block (MLAB)— ...

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... Tamper protection—comprehensive design protection to protect your valuable IP investments Enhanced advanced encryption standard (AES) design security features CvP Partial and dynamic reconfiguration of the FPGA Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and x16 configuration options Cyclone V Device Overview Description Description Altera Corporation 3 ...

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... Multiplier PLL 1 GPIO 1 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera Corporation Package Type F : FineLine BGA (FBGA Ultra FineLine BGA (UBGA) Embedded Hard IPs M : Micro FineLine BGA (MBGA hard PCIe or hard ...

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... U484 F484 F672 (19 mm) (23 mm) (27 mm) GPIO GPIO GPIO 224 224 — 224 224 — 224 240 — 240 240 336 240 224 336 I/O Features in Cyclone V Devices Altera Corporation 5 A9 120 2 F896 (31 mm) GPIO — — — 480 480 chapter. ...

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... The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs. 4 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. 5 For the number of LVDS channels in each package, refer to the Altera Corporation Transceiver Count memory controller ...

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... Optional Suffix Indicates specific device options or shipment method N : Lead-free packaging ES : Engineering sample FPGA Fabric Speed Grade 6 (fastest Member Code D7 149.5 7 F1152 (35 mm) XCVR GPIO XCVR — — — — — — — — — 9 — — 12 560 12 D9 301 Altera Corporation ...

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... If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Altera recommends that you use only full-duplex transceiver channels for CPRI, and up to eight full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels. Altera Corporation D5 29,080 ...

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... N : Lead-free packaging ES : Engineering sample FPGA Fabric Speed Grade 6 (fastest Member Code A5 85 32,075 41,509 128,300 166,036 3,970 5,140 480 87 174 6 3 288 188 72 1 I/O Features in Cyclone V Devices Altera Corporation 9 A6 110 621 112 224 6 3 288 188 72 1 chapter. ...

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... F : Maximum 2 hard PCIe controllers and 1 hard memory controller Family Signature 5C : Cyclone V Family Variant SX : SoC FPGA with 3-Gbps transceivers Member Code C2 : 25K logic elements C4 : 40K logic elements C5 : 85K logic elements C6 : 110K logic elements Altera Corporation Single- or Single- or dual-core dual-core U484 U672 (19 mm) ...

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... Dual-core Dual-core F896 (31 mm) FPGA GPIO HPS I/O — — — — 288 188 288 188 I/O Features in Cyclone V Devices 11 C6 110 41,509 166,036 5,140 621 112 224 288 188 Dual-core XCVR — — chapter. Altera Corporation ...

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... FPGA GPIO HPS I/O 17 The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs. 18 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Altera Corporation Package Type F : FineLine BGA (FBGA) Transceiver Count ...

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... Gen2. The CMU channels are not considered full-duplex channels. Cyclone V Device Overview Dual-core F896 (31 mm) FPGA GPIO HPS I/O 288 188 288 188 I/O Features in Cyclone V Devices Cyclone V Device Overview Member Code Dual-core XCVR chapter. Altera Corporation 13 ...

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... Cyclone V devices use ALM as the basic building block of the logic fabric. The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. Altera Corporation Code M281 M385 ...

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... Adaptive 5 LUT Full Adder Embedded Memory Capacity in Cyclone V Devices Multiplier Size (Bit) Three Two Two with accumulate One with accumulate 15 Cyclone V Device Overview Reg Reg Reg Reg on page standalone-17. DSP Block Resource Altera Corporation ...

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... C9 D5 Cyclone Cyclone Cyclone Cyclone Altera Corporation Independent Input and Output Variable-pre- Multiplications Operator cision DSP Block Multiplier Multiplier 198 132 150 450 300 156 468 312 ...

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... Altera Corporation 17 ...

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... The PLLs in the Cyclone V devices support the following features: Frequency synthesis On-chip clock deskew Jitter attenuation Counter reconfiguration Programmable output clock duty cycles PLL cascading Reference clock switchover Programmable bandwidth User-mode reconfiguration of PLLs Altera Corporation M10K Block RAM Bit (Kb) C2 140 1,400 C4 224 2,240 ...

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... The integrated multifunction support reduces the FPGA logic requirements 20,000 LEs for PCIe designs that require multiple peripherals. Cyclone V Device Overview OCT) for all I/O banks with OCT calibration to limit the termination T 19 Cyclone V Device Overview ) and programmable OD Altera Corporation ...

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... All Cyclone V devices support soft memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices for maximum flexibility. External Memory Performance Table 20: External Memory Interface Performance in Cyclone V Devices Interface DDR3 SDRAM DDR2 SDRAM LPDDR2 SDRAM Altera Corporation FPGA Device Host CPU PCIe Link Root Complex Local Local ...

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... The transceivers are positioned on the left outer edge of the device. The transceiver channels consist of the physical medium attachment (PMA), physical coding sublayer (PCS), and clock networks. Cyclone V Device Overview Cyclone V Device Overview Voltage (V) HPS Hard Controller (MHz) 1.5 1.35 1.8 1.5 1.2 21 400 400 400 400 333 Altera Corporation ...

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... Programmable deserialization and word alignment Equalization and pre-emphasis Ring oscillator transmit PLLs Input reference clock range Transceiver dynamic reconfiguration Altera Corporation I/O, LVDS, and Memory Interface Hard Memory Controller Hard Memory Controller I/O, LVDS, and Memory Interface Capability Driving capability Gbps Superior jitter tolerance Flexible deserialization width and configurable word alignment pattern ...

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... PIPE 2.0 interface to the core logic Custom PHY IP core with preset feature GbE receiver synchronization state machine Dedicated XAUI PHY IP core XAUI synchronization state machine for realigning four channels Custom PHY IP core with preset feature SRIO version 2.1-compliant x2 and x4 deskew state machine Altera Corporation ...

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... The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. 23 The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric. 24 High-voltage output mode (1000-BASE-CX) is not supported. 25 Pending characterization. Altera Corporation Data Transmitter Data Path Feature Rates(Gbps) 22 0.27 , 1.485, and 2.97 Custom PHY IP core with preset ...

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... Cyclone V Device Overview FPGA Fabric FPGA-to-HPS SDRAM HPS CPU1 Multiport ARM Cortex-A9 with NEON/FPU, DDR SDRAM 32 KB Instruction Cache, Controller 32 KB Data Cache, and with Memory Management Unit Optional ECC Altera Corporation 25 ® ) Advanced ...

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... The Virtual Target is a fast PC-based functional simulation of a target development system—a model of a complete development board that runs on a PC. The Virtual Target enables the development of device-specific production software that can run unmodified on actual hardware. Altera Corporation ® , and other operating systems will be available for the SoC FPGAs. For more information Altera sales team ...

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... Cyclone V Device Overview Design Se- Partial Recon- sion curity figuration Yes Yes — Yes Yes — Yes Yes — Yes Yes Yes Altera Corporation 27 ® solution, Remote Sys- tem Update Yes — Parallel flash loader ...

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... Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver substantial power savings 25% less power than equivalent soft implementations. Document Revision History Date December 2012 2012.12.28 Altera Corporation Data Max Clock Max Data Decompres- Width Rate ...

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... Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor Booting” on page 1–19, and “Hardware and Software Development” on page 1–20. Minor text edits. 1.0 Initial release. Cyclone V Device Overview Changes Altera Corporation 29 ...