5CSEBA6U23C7N Altera Corporation, 5CSEBA6U23C7N Datasheet - Page 19

• Manufacturer Part Number: 5CSEBA6U23C7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 4150 LABs 145 IO
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA6U23C7N

• Rohs: yes
• Number Of Logic Blocks: 4150
• Embedded Block Ram - Ebr: 621 kbit
• Number Of I/os: 145
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-672
• Distributed Ram: 5140 kbit
• Minimum Operating Temperature: 0 C

CV-51001
2012.12.28
Cyclone V Device Overview
FPGA General Purpose I/O
PCIe Gen1, Gen2, and Gen 3 Hard IP
Fractional PLL
In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up to
eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two
ways:
If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency
synthesis—removing the need for off-chip reference clock sources in your design.
The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose
fractional PLLs by the FPGA fabric.
Cyclone V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:
Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP that is designed for performance, ease-of-use,
and increased functionality. The PCIe hard IP consists of the MAC, data link, and transaction layers.
The PCIe hard IP supports PCIe Gen2 and Gen1 end point and root port for up to x4 lane configuration.
The PCIe Gen2 x4 support is PCIe-compatible.
The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the
following figure. The integrated multifunction support reduces the FPGA logic requirements by up to
20,000 LEs for PCIe designs that require multiple peripherals.
Low power mode for each fractional PLL
Dynamic phase shift
Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes
Reduce the number of oscillators that are required on your board by using fractional PLLs
Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies
from a single reference clock source
Programmable bus hold and weak pull-up
LVDS output buffer with programmable differential output voltage (V
pre-emphasis
On-chip parallel termination (R
impedance variation
On-chip dynamic termination that has the ability to swap between series and parallel termination,
depending on whether there is read or write on a common bus for signal integrity
Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop
(DLL) delay chain with fine and coarse architecture
T
OCT) for all I/O banks with OCT calibration to limit the termination
Cyclone V Device Overview
OD
) and programmable
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