5CSEBA6U23C7N Altera Corporation, 5CSEBA6U23C7N Datasheet - Page 23

• Manufacturer Part Number: 5CSEBA6U23C7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 4150 LABs 145 IO
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA6U23C7N

• Rohs: yes
• Number Of Logic Blocks: 4150
• Embedded Block Ram - Ebr: 621 kbit
• Number Of I/os: 145
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-672
• Distributed Ram: 5140 kbit
• Minimum Operating Temperature: 0 C

CV-51001
2012.12.28
Cyclone V Device Overview
PCS Features
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Table 23: Transceiver PCS Features for Cyclone V Devices
3-Gbps and 5-Gbps
Basic
PCIe Gen1
(x1, x2, x4)
PCIe Gen2
( x1, x2, x4)
GbE
XAUI
HiGig
SRIO 1.3 and 2.1
PCIe Gen2 is supported only for Cyclone V GT devices. The PCIe Gen2 x4 support is PCIe-compatible.
The Cyclone V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit interface, depending on
the transceiver data rate and protocol. Cyclone V devices contain PCS hard IP to support PCIe Gen1 and
Gen2, XAUI, Gbps Ethernet (GbE), Serial RapidIO
Most of the standard and proprietary protocols from 614 Mbps to 5.0 Gbps are supported.
PCS Support
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1.25 to 3.125
Rates(Gbps)
0.614 to 5.0
2.5 and 5.0
3.125
Data
1.25
3.75
Transmitter Data Path Feature
Phase compensation FIFO
Byte serializer
8B/10B encoder
Transmitter bit-slip
Dedicated PCIe PHY IP core
PIPE 2.0 interface to the core
logic
Custom PHY IP core with
preset feature
GbE transmitter
synchronization state
machine
Dedicated XAUI PHY IP core
XAUI synchronization state
machine for bonding four
channels
Custom PHY IP core with
preset feature
SRIO version 2.1-compliant
x2 and x4 channel bonding
®
(SRIO), and Common Public Radio Interface (CPRI).
Cyclone V Device Overview
Receiver Data Path Feature
Word aligner
Deskew FIFO
Rate-match FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensation
FIFO
Dedicated PCIe PHY IP core
PIPE 2.0 interface to the core
logic
Custom PHY IP core with
preset feature
GbE receiver synchronization
state machine
Dedicated XAUI PHY IP core
XAUI synchronization state
machine for realigning four
channels
Custom PHY IP core with
preset feature
SRIO version 2.1-compliant
x2 and x4 deskew state
machine
Altera Corporation
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