5SGXEA4K3F35I3LN Altera Corporation, 5SGXEA4K3F35I3LN Datasheet - Page 15

• Manufacturer Part Number: 5SGXEA4K3F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 432 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4K3F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 432
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Variable Precision DSP Block
Variable Precision DSP Block
Table 10. Variable Precision DSP Block Configurations
Table 11. Complex Multiplication with Variable Precision DSP Blocks
December 2012 Altera Corporation
Multiplier Size (bits)
Multiplier Size (bits)
18x18
27x27
36x36
18x18
18x25
18x36
27x27
9x9
Stratix V FPGAs feature the industry’s first variable precision DSP block that you can
configure to natively support signal processing with precision ranging from 9x9 to
36x36.
You can independently configure each DSP block at compile time as either a dual
18x18 multiply accumulate or a single 27x27 multiply accumulate. With a dedicated
64-bit cascade bus, you can cascade multiple variable precision DSP blocks to
implement even higher precision DSP functions efficiently.
variable precision is accommodated within a DSP block or by using multiple blocks.
Complex multiplication is common in DSP algorithms. One of the most popular
applications of complex multipliers is the fast Fourier transform (FFT) algorithm,
which increases precision requirements on only one side of the multiplier. The
variable precision DSP block is designed to support the FFT algorithm with a
proportional increase in DSP resources with precision growth.
multiplication with variable precision DSP blocks.
For FFT applications with high dynamic range requirements, only the Altera
MegaCore offers an option of single precision floating point implementation, with the
resource usage and performance similar to high-precision fixed point
implementations.
Other new features include:
■
■
■
■
■
■
■
1/3 of variable precision DSP block
1/2 of variable precision DSP block
64-bit accumulator, the largest in the industry
Hard pre-adder, available in both 18- and 27-bit modes
Cascaded output adders for efficient systolic FIR filters
Internal coefficient register banks
Enhanced independent multiplier operation
Efficient support for single- and double-precision floating point arithmetic
Ability to infer all the DSP block modes through HDL code using the Altera
Complete Design Suite
2 variable precision DSP blocks
1 variable precision DSP block
2 variable precision DSP blocks
3 variable precision DSP blocks
4 variable precision DSP blocks
4 variable precision DSP blocks
DSP Block Resources
DSP Block Resources
High precision fixed or single precision floating point
Accommodate bit growth through FFT stages
Very high precision fixed point
Medium precision fixed point
Single precision floating point
Highest precision FFT stages
Low precision fixed point
Resource optimized FFTs
Expected Usage
Expected Usage
Table 10
Table 11
Stratix V Device Overview
describes how
lists complex
®
FFT
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