5SGXEA4K3F35I3LN Altera Corporation, 5SGXEA4K3F35I3LN Datasheet - Page 16

• Manufacturer Part Number: 5SGXEA4K3F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 432 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4K3F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 432
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Page 16
Power Management
Incremental Compilation
Stratix V Device Overview
The variable precision DSP block is ideal for higher bit precision in high-performance
DSP applications. At the same time, the variable precision DSP block can efficiently
support the many existing 18-bit DSP applications, such as high definition video
processing and remote radio heads. Stratix V FPGAs, with the variable precision DSP
block architecture, are the only FPGA family that can efficiently support many
different precision levels, up to and including floating point implementations. This
flexibility results in increased system performance, reduced power consumption, and
reduced architecture constraints for system algorithm designers.
Stratix V devices leverage FPGA architectural features and process technology
advancements to reduce total power consumption by up to 30% when compared with
Stratix IV devices at the same performance level.
Stratix V devices continue to provide programmable power technology, introduced in
earlier generations of Stratix FPGA families. The Quartus II software PowerPlay
feature identifies critical timing paths in a design and biases core logic in that path for
high performance. PowerPlay also identifies non-critical timing paths and biases core
logic in that path for low power instead of high performance. PowerPlay
automatically biases core logic to meet performance and optimize power
consumption.
Additionally, Stratix V devices have a number of hard IP blocks that reduce logic
resources and deliver substantial power savings when compared with soft
implementations. The list includes PCIe Gen1/Gen2/Gen3, Interlaken PCS, hard I/O
FIFOs, and transceivers. Hard IP blocks consume up to 50% less power than
equivalent soft implementations.
Stratix V transceivers are designed for power efficiency. The transceiver channels
consume 50% less power than Stratix IV FPGAs. The transceiver PMA consumes
approximately 90 mW at 6.5 Gbps and 170 mW at 12.5 Gbps.
The Quartus II software incremental compilation feature reduces compilation time by
up to 70% and preserves performance to ease timing closure. Incremental compilation
supports top-down, bottom-up, and team-based design flows. Incremental
compilation facilitates modular hierarchical and team-based design flows where a
team of designers work in parallel on a design. Different designers or IP providers can
develop and optimize different blocks of the design independently, which you can
then import into the top-level project.
December 2012 Altera Corporation
Power Management