5SGXEA4K3F35I3LN Altera Corporation, 5SGXEA4K3F35I3LN Datasheet - Page 17

• Manufacturer Part Number: 5SGXEA4K3F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 432 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4K3F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 432
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Enhanced Configuration and CvP
Enhanced Configuration and CvP
Table 12. Configuration Modes for Stratix V Devices
December 2012 Altera Corporation
Active Serial (AS)
Passive Serial (PS)
Fast Passive
Parallel (FPP)
CvP
Partial
Reconfiguration
JTAG
Notes to
(1) Remote update support with the Parallel Flash Loader.
(2) The maximum clock rate is 125 MHz for x8 and x16 FPP, but only 100 MHz for x32 FPP.
Mode
Table
Partial Reconfiguration
12:
Slow POR
Stratix V device configuration is enhanced for ease-of-use, speed, and cost. Stratix V
devices support a new 4-bit bus active serial mode (ASx4). ASx4 supports up to a
400-Mbps data rate using small low-cost quad interface Flash devices. ASx4 mode is
easy to use and offers an ideal balance between cost and speed. Finally, the fast
passive parallel (FPP) interface is enhanced to support 8-, 16-, and 32-bit data widths
to meet a wide range of performance and cost goals.
You can configure Stratix V FPGAs using CvP with PCIe. CvP with PCIe divides the
configuration process into two parts: the PCIe hard IP and periphery and the core
logic fabric. CvP uses a much smaller amount of external memory (flash or ROM)
because CvP has to store only the configuration file for the PCIe hard IP and
periphery. The 100-ms power-up to active time (for PCIe) is much easier to achieve
when only the PCIe hard IP and periphery are loaded. After the PCIe hard IP and
periphery are loaded and the root port is booted up, application software running on
the root port can send the configuration file for the FPGA fabric across the PCIe link
where the file is loaded into the FPGA. The FPGA is then fully configured and
functional.
Table 12
Partial reconfiguration allows you to reconfigure part of the FPGA while other
sections continue to operate. This capability is required in systems where uptime is
critical because partial reconfiguration allows you to make updates or adjust
functionality without disrupting services. While lowering power and cost, partial
reconfiguration also increases the effective logic density by removing the necessity to
place FPGA functions that do not operate simultaneously. Instead, you can store these
functions in external memory and load them as required. This capability reduces the
size of the FPGA by allowing multiple applications on a single FPGA, saving board
space and reducing power.
Fast or
Yes
Yes
Yes
—
—
—
lists the configuration modes available for Stratix V devices.
Compression
Yes
Yes
Yes
—
—
—
Encryption
Yes
Yes
Yes
Yes
Yes
—
Remote
Update
Yes
Yes
Yes
—
—
(1)
8, 16, 32
1, 2, 4, 8
Width
Data
1, 4
16
1
1
Max Clock
Rate (MHz)
125
100
125
125
—
33
(2)
Stratix V Device Overview
Max Data Rate
(Mbps)
3,000
3,000
2,000
125
400
33
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