ST72C334J2B6 STMicroelectronics, ST72C334J2B6 Datasheet - Page 56

• Manufacturer Part Number: ST72C334J2B6
• Description: 8-bit Microcontrollers - MCU Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334J2B6

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.2 V to 5.5 V
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 8
• Data Rom Size: 256 B
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Program Memory Type: Flash
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 3.2 V

ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, out-
put compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
56/153
At t0
At t0 + t
Beginning of the sequence
Sequence completed
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
Read
MS Byte
Read
LS Byte
instructions
Other
Returns the buffered
LS Byte value at t0
is buffered
LS Byte
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
14.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.