AD6657AEBZ

Manufacturer Part NumberAD6657AEBZ
DescriptionData Conversion IC Development Tools 11 Bit 200 Msps Quad IF Receiver
ManufacturerAnalog Devices
TypeADC
SeriesAD6657A
AD6657AEBZ datasheet
 


Specifications of AD6657AEBZ

RohsyesProductEvaluation Boards
Tool Is For Evaluation OfAD6657AInterface TypeSPI, USB
Operating Supply Voltage6 VDescription/functionQuad IF receiver with noise shaping requantizer
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Operating Supply Current2 AFactory Pack Quantity1
For Use WithHSC-ADC-EVALCZ  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Page 1/36

Download datasheet (2Mb)Embed
Next
Data Sheet
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The
AD6657A
is an 11-bit, 200 MSPS, quad channel intermediate
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Quad IF Receiver
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD6657A
14
VIN+A
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
VIN–A
VCMA
14
VIN+B
NOISE SHAPING
PIPELINE
REQUANTIZER
ADC
VIN–B
VCMB
14
VIN+C
NOISE SHAPING
PIPELINE
REQUANTIZER
ADC
VIN–C
VCMC
14
VIN+D
NOISE SHAPING
PIPELINE
REQUANTIZER
ADC
VIN–D
VCMD
REFERENCE
SERIAL PORT
SCLK
SDIO
CSB
Figure 1.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the
AD6657A
supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22%, 33%,
or 36% of the sample clock. For example, with a sample clock
rate of 185 MSPS, the
AD6657A
can achieve up to 76.0 dBFS
SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS
SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS
SNR for a 65 MHz bandwidth in the 36% mode.
(General Description continued on Page 3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD6657A
DRGND
DCO±AB
11
DO±AB
PORT A
11
D10±AB
DCO±CD
11
DO±CD
PORT B
11
D10±CD
MODE
CLOCK
SYNC
DIVIDER
PDWN
CLK+
CLK–
www.analog.com