AD6657AEBZ Analog Devices, AD6657AEBZ Datasheet - Page 23

• Manufacturer Part Number: AD6657AEBZ
• Description: Data Conversion IC Development Tools 11 Bit 200 Msps Quad IF Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6657Ar

Specifications of AD6657AEBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6657A
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: Quad IF receiver with noise shaping requantizer
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNR
can be calculated by
In the equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as shown in Figure 49.
In cases where aperture jitter may affect the dynamic range of
the AD6657A, treat the clock input as an analog signal. Separate
power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step. Refer to the
Application Note
tion about jitter performance as it relates to ADCs (available at
www.analog.com).
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the
rate (see Figure 50). The digital power dissipation does not vary
significantly because it is determined primarily by the DRVDD
supply and the bias current of the LVDS drivers.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 50 was
obtained using the same operating conditions as those used in
the Typical Performance Characteristics section, with a 5 pF
load on each output driver.
SNR
80
75
70
65
60
55
50
HF
1
LF
= −10log[(2π × f
) at a given input frequency (f
Figure 49. SNR vs. Input Frequency and Jitter
and
AN-756 Application Note
INPUT FREQUENCY (MHz)
10
AD6657A
IN
× t
JRMS
)
2
+ 10
is proportional to its clock
100
IN
(−SNR LF /10)
) due to jitter (t
for more informa-
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
]
AN-501
1k
JRMS
Rev. 0 | Page 23 of 36
)
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the
mode. In this state, the ADC typically dissipates 4.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD6657A
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode; shorter power-down cycles
result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Descriptions section for more details.
CHANNEL/CHIP SYNCHRONIZATION
The
synchronization options for synchronizing the clock divider. The
clock divider sync feature is useful for guaranteeing synchronized
sample clocks across multiple ADCs.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, externally synchronize the SYNC input signal to
the input clock signal, meeting the setup and hold times shown
in Table 5. Drive the SYNC input using a single-ended CMOS
type signal.
AD6657A
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190
Figure 50. Power and Current vs. Sampling Frequency
to its normal operating mode. Note that PDWN is
has a SYNC input that offers the user flexible
SAMPLING FREQUENCY (MSPS)
TOTAL POWER
AD6657A
I
DRVDD
I
AVDD
is placed in power-down
AD6657A
200
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0