IS41LV16100B-60TLI ISSI, Integrated Silicon Solution Inc, IS41LV16100B-60TLI Datasheet - Page 4

• Manufacturer Part Number: IS41LV16100B-60TLI
• Description: IC DRAM 16MBIT 60NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: EDOr

Specifications of IS41LV16100B-60TLI

• Format - Memory: RAM
• Memory Type: DRAM - EDO
• Memory Size: 16M (1M x 16)
• Speed: 60ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 10b
• Access Time (max): 60ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 170mA
• Pin Count: 44
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS41LV16100B
Functional Description
The IS41LV16100B is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS). RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
The IS41LV16100B has two CAS controls, LCAS and UCAS.
The LCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
the other 1M x 16 DRAMs. The key difference is that each CAS
controls its corresponding I/O tristate logic (in conjunction with
OE and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41LV16100B CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100B both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
cycle must not be initiated until the minimum precharge
time t
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by t
Data Out becomes valid only when t
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
2. Using a CAS-before-RAS refresh cycle. CAS-before-
4
with RAS at least once every 128 ms. Any read, write, read-
modify-write or RAS-only cycle refreshes the addressed row.
RAS refresh is activated by the falling edge of RAS,
RP
, t
CP
has elapsed.
RAS
time has expired. A new
RAC
, t
AA
, t
CAC
Integrated Silicon Solution, Inc. — www.issi.com —
and t
OEA
AR
.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
retention mode at the extended refresh period of 128 ms. i.e.,
125 µs per row when using distributed CBR refreshes. The
feature also allows the user the choice of a fully static, low
power data retention mode. The optional Self Refresh feature
is initiated by performing a CBR Refresh cycle and holding
RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 1,024 rows must be refreshed within the
average internal refresh rate, prior to the resumption of
normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is equiva-
lent to that of the fast page mode in that case.
Power-On
After application of the V
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
During power-on, it is recommended that RAS track with
V
The Self Refresh allows the user a dynamic refresh, data
DD
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
or be held at a valid V
IH
DD
to avoid current surges.
supply, an initial pause of
ISSI
1-800-379-4774
12/11/06
Rev. C
®