IS41LV16100B-60TLI ISSI, Integrated Silicon Solution Inc, IS41LV16100B-60TLI Datasheet - Page 9

• Manufacturer Part Number: IS41LV16100B-60TLI
• Description: IC DRAM 16MBIT 60NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: EDOr

Specifications of IS41LV16100B-60TLI

• Format - Memory: RAM
• Memory Type: DRAM - EDO
• Memory Size: 16M (1M x 16)
• Speed: 60ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 10b
• Access Time (max): 60ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 170mA
• Pin Count: 44
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS41LV16100B
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF (V
Input timing reference levels:
Output timing reference levels:
Notes:
10. Operation with the t
11. Operation within the t
12. Either t
13. t
14. t
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
19. The I/Os are in open during READ cycles once t
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
12/11/06
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
2. V
3. In addition to meeting the transition rate specification, all input signals must transit between V
4. If CAS and RAS = V
5. If CAS = V
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
8. Assumes that t
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
V
monotonic manner.
by the amount that t
output buffer, CAS and RAS must be pulsed for t
greater than the specified t
greater than the specified t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
(MIN), t
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to V
WRITE or READ-MODIFY-WRITE is not possible.
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after t
MODIFY-WRITE cycles.
OFF
WCS
IH
IL
(or between V
(MIN) and V
IH
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
, t
) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
RWD
RCH
AWD
, t
IL
or t
AWD
, data output may contain data from the last valid READ cycle.
≤ t
RRH
AWD
RCD
RCD
IL
and t
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IL
must be satisfied for a READ cycle.
(MIN) and t
≤ t
≤ t
and V
RCD
IH
RCD
CWD
RAD
, data output is High-Z.
RCD
RCD
(MAX) limit ensures that t
exceeds the value shown.
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
(MAX) limit ensures that t
IH
(MAX).
(MAX). If t
RAD
) and assume to be 1 ns for all inputs.
RCD
CWD
(MAX) limit, access time is controlled exclusively by t
(MAX) limit, access time is controlled exclusively by t
V
OEH
IH
V
≤ t
OH
= 2.0V, V
is met.
RCD
CWD
= 2.0V, V
is greater than the maximum recommended value shown in this table, t
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
DD
= 3.3V ±10%)
IL
= 0.8V (V
CP
OD
RAC
OL
RCD
.
or t
= 0.8V
(MAX) can be met. t
(MAX) can be met. t
OFF
occur.
DD
1-800-379-4774
= 3.3V ±10%)
OD
and t
RCD
OEH
RAD
(MAX) is specified as a reference point only; if t
met (OE HIGH during WRITE cycle) in order to ensure
(MAX) is specified as a reference point only; if t
AA
CAC
.
REF
.
refresh requirement is exceeded.
IH
and V
IL
(or between V
OH
or V
ISSI
RAC
OL
IL
.
will increase
and V
RWD
WCS
≤ t
≤ t
IH
IH
RCD
RAD
) in a
RWD
and
WCS
®
is
is
9