MT46H32M32LFJG-6:A TR Micron Technology Inc, MT46H32M32LFJG-6:A TR Datasheet - Page 7

• Manufacturer Part Number: MT46H32M32LFJG-6:A TR
• Description: IC DDR SDRAM 1GBIT 168VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H32M32LFJG-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 1G (32M x 32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 168-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3:
PDF: 09005aef833508fb/Source: 09005aef83350d72
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
A12, H23, K1, Y23, AA23 A12, H23, K1, Y23, AA23
U23, U22, T23, T22, R23,
A14, B16, A16, B19, A19
R22, P23, P22, N23, N22
A4, A7, A10, A15, A18,
B3, A3, B5, A5, B8, A8,
B9, A9, B13, A13, B14,
W23, W22, V23, V22,
C23, E1, F23, H1
AB21, AC21
M22, M23
x16 Balls
A11, B11
A17, A6
J22, J23
B17, B6
AC14
K23
L22
L23
x16/x32 LPDDR Ball Descriptions
Notes:
G23, G22, E23, E22, D23,
A19, B19, A16, B16, A14,
U22, T23, T22, R23, R22,
A4, A7, A10, A15, A18,
A8, B8, A5, B5, A3, B3,
D22, A21, B21, A9, B9,
B14, A13, B13, D1, D2,
W22, V23, V22, U23,
F1, F2, G1, G2, J1, J2
1. Balls marked RFU may or may not be connected internally. These balls should not be used.
P23, P22, N23, N22
A20, A6, A17, C1
B20, B6, B17, C2
C23, E1, F23, H1
Contact factory for details.
AB21, AC21
x32 Balls
M22, M23
A11, B11
J22, J23
AC14
K23
L22
L23
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
LDQS, UDQS
CKE0, CKE1
LDM, UDM
CS0#, CS1#
BA0, BA1
DQ[15:0]
DQ[31:0]
DQS[3:0]
Symbol
DM[3:0]
CK, CK#
A[13:0]
A[12:0]
Vddq
CAS#
RAS#
(x16)
(x32)
(x16)
(x32)
(x16)
(x32)
(x16)
(x32)
WE#
Vdd
TQ
7
Output Temperature sensor output: TQ HIGH when
output
output
Supply
Supply
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Type
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Address inputs: Specify row/column addresses.
Also used to load the mode registers. The
maximum address is determined by density
and configuration. Consult the product data
sheet for the maximum address for a given
density and configuration.
Unused address pins become RFU
Bank address inputs: Specifies one of the 4
banks.
Column select: Specifies the command to
execute.
CK is the system clock. CK and CK# are
differential clock inputs. All address and
control signals are sampled and referenced on
the crossing of the rising edge of CK with the
falling edge of CK#.
Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is
considered RFU for single products.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is
considered RFU for single products
Data mask: Determines which bytes are
written during WRITE operations.
For x16 LPDDR, unused DM balls become
DNU.
Row select: Specifies the command to
execute.
Write enable: Specifies the command to
execute.
Data bus: Data inputs/outputs. DQ[31:16] are
DNU for x16 LPDDR devices.
Note: For dual-die devices, the I/O capacitance
will be twice the value shown in the packaged
data sheet.
Data strobe: Coordinates read/write transfers
of data; one DQS per DQ byte.
LPDDR T
Vdd: LPDDR power supply.
Vddq: LPDDR I/O power supply.
J
exceeds 85°C.
Description
©2008 Micron Technology, Inc. All rights reserved.
SDRAM Addendum
1
.
Preliminary