M29W160EB70N6F NUMONYX, M29W160EB70N6F Datasheet - Page 12

• Manufacturer Part Number: M29W160EB70N6F
• Description: IC FLASH 16MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W160EB70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Package: 48TSOP
• Cell Type: NOR
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 2|16KByte x 1|32KByte x 1|64KByte x 31
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M29W160ET, M29W160EB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 12, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
Table 2. Bus Operations, BYTE = V
Note: X = V
12/42
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Operation
IH
IH
IL
.
. The Data Inputs/Outputs will output the
or V
IH
.
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IH
, during the whole Bus
V
V
V
V
V
IL
G
X
IH
IH
IL
IL
IL
, to Chip Enable
IL
V
V
V
V
V
W
X
IH
IH
IH
IH
IL
IH
, the
Cell Address
Command Address
X
X
A0 = V
Others V
A0 = V
Others V
DQ15A–1, A0-A19
Address Inputs
IH
IL
, A1 = V
, A1 = V
IL
IL
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require V
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
or V
or V
IH
IH
IL
IL
, A9 = V
, A9 = V
CC3
, for Program or Erase operations un-
ID
ID
CC
,
,
± 0.2V. For the Standby current
DQ14-DQ8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Inputs/Outputs
CC2
, Chip Enable should
C4h (M29W160ET)
49h (M29W160EB)
Data Output
Data Input
DQ7-DQ0
Hi-Z
Hi-Z
20h
CC
CC2
ID
± 0.2V)
. The
to be