X28HC256JIZ-15T1 Intersil, X28HC256JIZ-15T1 Datasheet
X28HC256JIZ-15T1
Specifications of X28HC256JIZ-15T1
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X28HC256JIZ-15T1 Summary of contents
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... P-P ™ cell 256kBIT EEPROM ARRAY I/O BUFFERS AND LATCHES I Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ...
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... X28HC256DM-12 RR X28HC256DMB-12 C X28HC256DMB-12 X28HC256EI-12 X28HC256EI-12 RR X28HC256EM-12 X28HC256EM-12 RR X28HC256EMB-12 C X28HC256EMB-12 X28HC256FMB-12 C X28HC256FMB-12 X28HC256J-12* X28HC256J-12 RR X28HC256JZ-12* (Note) X28HC256J-12 ZRR X28HC256JI-12* X28HC256JI-12 RR X28HC256JIZ-12* (Note) X28HC256JI-12 ZRR X28HC256KI-12 X28HC256KI-12 RR X28HC256KM-12 X28HC256KM-12 RR X28HC256KMB-12 C X28HC256KMB-12 X28HC256P-12 X28HC256P-12 RR X28HC256PZ-12 (Note) X28HC256P-12 RRZ X28HC256PI-12 X28HC256PI- X28HC256 ACCESS TIME TEMP. RANGE (ns) (° ...
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... X28HC256EM-90 X28HC256EM-90 RR X28HC256EMB-90 C X28HC256EMB-90 X28HC256FI-90 X28HC256FI-90 RR X28HC256FM-90 X28HC256FM-90 RR X28HC256FMB-90 C X28HC256FMB-90 X28HC256J-90* X28HC256J-90 RR X28HC256JZ-90* (Note) X28HC256J-90 ZRR X28HC256JI-90* X28HC256JI-90 RR X28HC256JIZ-90* (Note) X28HC256JI-90 ZRR X28HC256JM-90* X28HC256JM-90 RR X28HC256KM-90 X28HC256KM-90 RR X28HC256KMB-90 C X28HC256KMB-90 X28HC256P-90 X28HC256P-90 RR X28HC256PZ-90 (Note) X28HC256P-90 RRZ X28HC256PI-90 X28HC256PI-90 RR X28HC256PIZ-90 (Note) X28HC256PI-90 RRZ X28HC256S-90* ...
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... Pin Descriptions Addresses ( The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations ...
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... Page Write Operation The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host ...
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DATA Polling I/O 7 LAST WRITE I WRITE DATA WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS COMPARE? YES X28HC256 READY ...
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... Software Data Protection The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits ...
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Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence ...
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... Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os ...
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... This parameter is periodically sampled and not 100% tested. 10 X28HC256 Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. TEST CONDITIONS All I/O’ ...
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Capacitance +25° 1MHz, V SYMBOL C (Note 9) Input/output capacitance I/O C (Note 9) Input capacitance IN Endurance and Data Retention PARAMETER Endurance Data retention AC Conditions of Test Input pulse levels Input rise and ...
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AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified. PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z ...
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Write Cycle Limits PARAMETER Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery (page write only) Data ...
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... Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the controlled write cycle timing ...
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DATA Polling Timing Diagram (Note 11) ADDRESS OEH I Toggle Bit Timing Diagram (Note 11 OEH OE HIGH Z I I/O 6 NOTE: ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -A- -D- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...
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Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) PIN (1) 0.056 (1.42) 0.042 (1.07) IDENTIFIER 0.050 (1.27) TP 0.048 (1.22 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN 0.025 (0.64) MIN VIEW ...
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Ceramic Pin Grid Array Package (CPGA) Typ. 0.100 (2.54) All Leads 0.660 (16.76) 0.640 (16.26) NOTE: All dimensions in inches (in parentheses in millimeters). 18 X28HC256 G28.550x650A 28 LEAD CERAMIC PIN GRID ARRAY PACKAGE ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...