MT41J128M8HX-187E:D TR Micron Technology Inc, MT41J128M8HX-187E:D TR Datasheet - Page 148

• Manufacturer Part Number: MT41J128M8HX-187E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J128M8HX-187E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1377-1

Figure 96: Data Input Timing
PRECHARGE
SELF REFRESH
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
DQS, DQS#
Input A10 determines whether one bank or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
The DRAM must be idle with all banks in the precharge state (
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see “On-Die Termination (ODT)” on page 160 for timing
requirements). If R
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH
command internally within the
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
specifications) when self refresh mode is entered. If the clock remains stable and the
frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self
refresh mode after
than when CKE was registered LOW). Since the clock remains stable in self refresh mode
(no frequency change),
altered during self refresh mode (turned-off or frequency change), then
t
prior to altering the clock's frequency. Prior to exiting self refresh mode,
satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for
is required for the completion of any internal refresh that is already in progress and must
be satisfied before a valid command not requiring a locked DLL can be issued to the
device.
CKSRX must be satisfied. When entering self refresh mode,
DM
DQ
t
XS is also the earliest time self refresh reentry may occur (see Figure 97 on
t WPRE
TT
t
CKESR is satisfied (CKE is allowed to transition HIGH
_
NOM
t
CKSRE and
DI
b
and R
t DQSH
t DS
148
t
CKE period when it enters self refresh mode.
TT
t DQSL
_
WR
t
t DH
CKSRX are not required. However, if the clock is
Micron Technology, Inc., reserves the right to change products or specifications without notice.
are disabled in the mode registers, ODT can be a
1Gb: x4, x8, x16 DDR3 SDRAM
t
CKSRE must be satisfied
Transitioning Data
t
©2006 Micron Technology, Inc. All rights reserved.
RP is satisfied and no
t
t
CKSRX must be
CKSRE and
t
Operations
CKESR later
t WPST
t
XS time.
Don’t Care
t
t
CK
XS