MT41J128M8HX-187E:D TR Micron Technology Inc, MT41J128M8HX-187E:D TR Datasheet - Page 151

• Manufacturer Part Number: MT41J128M8HX-187E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J128M8HX-187E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1377-1

Power-Down Mode
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Table 73:
DRAM Status
Idle or active
Idle or active
Power-down
Active
Active
Active
Active
Active
Idle
Idle
Command to Power-Down Entry Parameters
WRITEAP: BL8OTF, BL8MRS,
Last Command Prior to
Notes:
WRITE: BL8OTF, BL8MRS,
MODE REGISTER SET
WRITEAP: BC4MRS
READ or READAP
WRITE: BC4MRS
PRECHARGE
CKE LOW
ACTIVATE
REFRESH
REFRESH
BC4OTF
BC4OTF
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR,
ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of
the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or
REFRESH) are in progress. However, the power-down I
cable until such operations have been completed. Depending on the previous DRAM
state and the command issued prior to CKE going LOW, certain timing constraints must
be satisfied (as noted in Table 73). Timing diagrams detailing the different power-down
mode entry and exits are shown in Figure 98 on page 152 through Figure 107 on
page 157.
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchro-
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until
at which time all specified input/output buffers will be disabled. The DLL should be in a
locked state when power-down is entered for the fastest power-down exit timing. If the
DLL is not locked during power-down entry, the DLL must be reset after exiting power-
down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down mode.
Precharge power-down mode must be programmed to exit with either a slow exit mode
or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in
slow exit mode or kept on in fast exit mode.
The DLL remains on when entering active power-down as well. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to “Asynchronous ODT Mode” on page 172 for detailed ODT usage requirements in slow
exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 74 on page 152.
nous
CKE goes HIGH.
1
t
ANPD prior to CKE going LOW and remains asynchronous until
Parameter (Min)
t
t
t
WRAPDEN
t
t
MRSPDEN
t
ACTPDEN
t
REFPDEN
WRPDEN
RDPDEN
PRPDEN
t
XPDLL
151
Greater of 10
WL + 4
WL + 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WL + 4
WL + 2
Parameter Value
RL + 4
t
t
CK + WR + 1
CK + WR + 1
t
t
t
CK +
CK +
1
1
1
MOD
t
CK + 1
t
t
t
1Gb: x4, x8, x16 DDR3 SDRAM
CK
CK
CK
t
CK or 24ns
t
t
WR/
WR/
t
CK
DD
t
t
CK
CK
t
t
CK
CK
specifications are not appli-
t
CPDED has been satisfied,
©2006 Micron Technology, Inc. All rights reserved.
Figure 105 on page 156
Figure 106 on page 156
Figure 101 on page 154
Figure 102 on page 154
Figure 102 on page 154
Figure 103 on page 155
Figure 103 on page 155
Figure 104 on page 155
Figure 108 on page 157
Figure 107 on page 157
t
ANPD +
Figure
Operations
t
XPDLL after