MT41J128M8HX-187E:D TR Micron Technology Inc, MT41J128M8HX-187E:D TR Datasheet - Page 29

• Manufacturer Part Number: MT41J128M8HX-187E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J128M8HX-187E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1377-1

Electrical Specifications – I
Table 9:
Table 10:
Table 11:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Switching for Address (Row/Column) and Command Signals (CS#, RAS#, CAS#, and/or WE#)
Switching for Data Pins (DQ, DQS, DM)
Address (row/column)
Bank address
Command
(CS#, RAS#, CAS#, WE#)
Data strobe (DQS)
Data (DQ)
Data masking (DM)
I
Definition of Switching for Command and Address Input Signals
Definition of Switching for Data Pins
DD
Measurement Conditions Reference
The following definitions are used within the I
• LOW: V
• Stable: Inputs are stable at a HIGH or LOW level
• Floating: Inputs are V
• Switching: See Tables 10 and 11
Table Number
Table 13 on page 31
Table 14 on page 33
Table 15 on page 35
Table 16 on page 37
Table 17 on page 38
If not otherwise stated, inputs are stable at HIGH or LOW during 4 clocks and then change to
the opposite value (Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax . . . )
If not otherwise stated, the bank addresses should be switched in a similar fashion as the
row/column addresses
Define command background pattern = D D D D D D D D D D D D . . . where:
D = (CS#, RAS#, CAS#, WE#) = (HIGH, LOW, LOW, LOW)
D = (CS#, RAS#, CAS#, WE#) = (HIGH, HIGH, HIGH, HIGH)
If other commands are necessary (ACTIVATE for I
pattern command is substituted by the respective CS#, RAS#, CAS#, and WE# levels of the
necessary command
Data strobe is changing between HIGH and LOW after every clock cycle
Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for
DQ signals, which means that data DQ is stable during one clock
No switching; DM must always be driven LOW
IN
Electrical Specifications – I
≤ V
IL
DD
(
AC
) MAX; HIGH: V
Specifications and Conditions
REF
= V
29
DD
Q/2
Measurement Conditions
I
I
I
I
I
DD
DD
DD
DD
DD
IN
0 and I
2Ps, I
4R, I
5B, I
7 (see Table 18 on page 38)
≥ V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
IH
DD
4W
6, I
(
2Pf, I
AC
DD
1
DD
DD
DD
) MIN
1Gb: x4, x8, x16 DDR3 SDRAM
6ET
0 or READ for I
DD
Specifications and Conditions
measurement tables:
2Q, I
DD
2N, I
DD
©2006 Micron Technology, Inc. All rights reserved.
DD
3P, and I
4R), the background
DD
3N