DSM2190F4V-15T6 STMicroelectronics, DSM2190F4V-15T6 Datasheet
DSM2190F4V-15T6
Specifications of DSM2190F4V-15T6
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DSM2190F4V-15T6 Summary of contents
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... Programmable Security Bit blocks access of de- vice programmers and readers Zero-Power Technology – As low standby current Packaging software...Free – 52-pin PQFP or 52-pin PLCC Flash Memory Speed, Endurance, Retention +85 C – 150 ns, 100K cycles, 15 year retention DSM2190F4V PQFP52 (T) PLCC52 (K) TM cable with PC 1/61 ...
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... I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Security and NVM Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Specifying the Memory Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erasing Flash Memory ...
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... Table: CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table: Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table: Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: Assignments – ...
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... JTAG programming techniques for both manufac- turing and the field. On-chip integrated memory decode logic makes it easy to map dual banks of Flash memory to the ADSP-2191 in a variety of ways for bootloading, code execution, data re- cording, code swapping, and parameter storage. JTAG ISP reduces development time, simplifies manufacturing flow, and lowers the cost of field up- grades ...
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... Table 1. DSM2190F4V DSP Memory System Devices Main Flash Part Number Memory 256KBytes = ...
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... DSM Main Flash or Secondary flash memories. Main Flash Memory The 2M bit (256K x 8) Flash memory is divided into eight equally-sized 32K byte sectors that are indi- vidually selectable through the Decode PLD. Each Flash memory sector can be located at any ad- dress as defined by the user with PSDsoft Ex- press ...
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... Memory Page Register This 8-bit register can be loaded and read by the DSP at runtime as one of the csiop registers. Its outputs feed directly into the PLDs. The page reg- ister can be used for special memory mapping re- quirements and also for general logic. DSM2190F4 DSM2190F4 ...
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... Port C, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. 8/61 The FlashLINK available from STMicroelectronics for $59USD and PSDsoft Express software is available at no charge from www.st.com/psm . That is all that is needed to program a DSM device using the paral- lel port on any PC or note-book. See section titled “ ...
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... CPLD output (External Chip Select). Does not consume Output Macrocells. 4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD. 5. Pin PD2 can optionally be configured as CSI, an active low Chip Select Input to select Flash memory. Flash memory is disabled to conserve more power when CSI is logic high. Can PD0-2 I/O connect CSI to ADSP-218X PWDACK output signal ...
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DSM2190F4 TYPICAL CONNECTIONS Figure 6 shows a typical connection scheme. Many connection possibilities exist since many DSM pins are multipurpose. This scheme illus- trates the use of a combined function (functions as and ), and many I/O pins. It BMS ...
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Figure 6. Typical Connections CONNECTOR JTAG DSM ohm 10k DSM2190F4 CONNECTOR JTAG DSP 11/61 ...
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... DSM memory and I/O depending on system requirements. The DPLD allows complete mapping flexibility. Figure 7 shows one possible system memory map. In this case, the DSP will bootload (via DMA) the contents of Main Flash memory upon reset. The Secondary Flash memo- ry can be used for parameter storage or additional code storage ...
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... Figure 7. Typical System Memory Map DSP Boot Memory Space (BMS) 56000-57FFF csboot, 8KB 2nd Flash 54000-55FFF csboot, 8KB 2nd Flash 52000-53FFF csboot, 8KB 2nd Flash 50000-51FFF csboot, 8KB 2nd Flash 4FFFF 32K bytes Main Flash 48000 47FFF 32K bytes Main Flash ...
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... PSDsoft Express and-click environment. PSDsoft Express generate Hardware Definition Language (HDL) Figure 8. HDL Statements Generated from PSDsoft Express to Implement Memory Map csiop = ((address >= ^h2000) & (address <= ^h20FF) & (!_ioms)); fs0 = ((address >= ^h10000) & (address <= ^h17FFF) & (!_bms)); fs1 = ((address >= ^h18000) & (address <= ^h1FFFF) & (!_bms)); ...
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... Select I/O Port). Table 4 lists the 27 registers and their offsets (in hexadecimal) from the csiop base address needed to access individ- ual DSM control and status registers. The DSP will access these registers in I/O memory space using Table 4. CSIOP Registers and their Offsets (in hexadecimal) Register Name Port B ...
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... DSP may read code from one array while sending instructions to the other. After a Flash memory array is programmed (writ- ten) it will go to “Read Array” mode, then the DSP can read from Flash memory just as if would from any 8-bit ROM or SRAM device. ...
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... DSP writes command sequence to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. The byte 30h must be addressed to one of the other Flash memory segments (FS0 - FS7) for each additional segment (write 30h to any address within a desired sector). No more than 80uS can elapse between subsequent additional sector erase commands. ...
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... Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be veri- fied. The read operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status can also be read by ( FS0-FS7 ...
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... Programming Flash Memory When a byte of Flash memory is programmed, in- dividual bits are programmed to logic 0. You can- not program a bit in Flash memory to a logic 1 once it has been programmed to a logic 0. A bit must be erased to logic 1, and programmed to log That means Flash memory must be erased prior to being programmed ...
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... It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 10 still applies ...
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... Flash Memory”, on page 19. The Error Flag (DQ5) bit returns there has been an Erase Failure (maximum number of Erase cycles have been executed not necessary to program the memory with 00h because the device automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction se- quence, the Flash memory does not accept any in- struction sequences ...
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... Bit 7 Bit 6 Bit 5 Sec7_Prot Sec6_Prot Sec5_Prot Note: Bit Definitions: Sec<i>_Prot 1 = Flash memory sector <i> is write protected. Sec<i>_Prot 0 = Flash memory sector <i> is not write protected. Table 8. Secondary Flash Memory Protection/Security Bit Register Definition Bit 7 Bit 6 Bit 5 Security_Bit not used not used Note: Security_Bit = 1, device is secured. ...
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... PG7) are inputs to the DPLD decoder and can be included in the Sector Select ( FS0-FS7 or CSBOOT0-CSBOOT3 ) equations. See Figure 12. If memory paging is not needed not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic ...
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... DSM2190F4 The DPLD performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and I/O ports. The DPLD can generates External Chip Select (ECS0-ECS2) signals on Port D. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic ...
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... The DPLD, shown in Figure 14, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: 8 Main Flash memory Sector Select ( FS0-FS7 ) signals with three product terms each 4 Secondary Flash memory Sector Select ( CSBOOT0-CSBOOT3 ) signals with three product terms each Figure 14 ...
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DSM2190F4 COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. See application note AN1171 for details on how to ...
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The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block ...
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... Port Input 28/61 Loading and Reading the Output Macrocells (OMCs). Each of the two OMC blocks (8 OMCs each) occupies a memory location in the DSP ad- dress space, as defined in the csiop block MCELLAB0-7 and MCELLBC0-7 (see Table 4). The flip-flops in each of the 16 OMCs can be load- ed from the data bus by a DSP. Loading the OMCs with data from the DSP takes priority over internal functions ...
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The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Out- put Macrocells (OMC). The default ...
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... DSP address, data, and control signals connect directly to the DSM device. See Figure 6 for typical connections. DSP address, data and control signals are routed to Flash memory, I/O control ( csiop ), OMCs, and IMCs within the DMS. The DSP address range for each of these components is specified in PSDsoft TM Express ...
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Direction Registers, and port pin input are all connected to the Port Data Buffer (PDB). The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array ...
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DSM2190F4 port. The three Port Configuration Registers (PCR), are shown in Table 12. Default is logic 0. Table 12. Port Configuration Registers (PCR) Register Name Port Data In B,C,D Data Out B,C,D Direction B,C,D 1 B,C,D Drive Select Note: 1. ...
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Table 16. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note Not Applicable. Figure 20. Port B ...
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DSM2190F4 Figure 21. Port C Structure DATA OUT REG MCELLBC [ 7:0 ] READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD - INPUT Port C – Functionality and ...
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... D Q CPLD-INPUT PSD Chip Select Input (CSI, PD2). Driving this signal logic High disables the Flash memory, putting it in standby mode. External Chip Select. The DPLD also provides three External Chip Select outputs (ESC0-2) on Port D pins that can be used to select external de- vices as defined in PSDsoft Express ...
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DSM2190F4 Figure 23. Port D External Chip Select Signals 36/61 ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 ...
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... POWER MANAGEMENT The device offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: All memory blocks in the device are built with zero-power management technology. Zero- power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current) ...
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... PD2) is High. CSI and the PMMR2 register. Note: CNTL0 and CNTL1 (DSP nently routed to the Flash memory array and can- not be blocked from the array by the PMMR registers (that’s why WR and RD signals do not have to be specified in PSDsoft Express for Flash memory segment chip-select equations for FS0 - FS7) ...
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... I/O Pin, Register and PLD Status at Reset. Ta- ble 19 shows the I/O pin, register and PLD status during Power On Reset, warm reset and Power- t OPR The Flash memory is reset to the Read Array mode upon Power-up. Sector Select FS0-FS7 must all be Low, Write Strobe ( NLNH-PO ...
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... Port C, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. See Table 20. The FlashLINK ming cable available from STMicroelectronics for $59USD and PSDsoft Express software that is available at no charge from www.st.com/psm is all that is needed to program a DSM device using the parallel port on any PC or laptop ...
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... DSM2190F4V devices and a wired- OR connection of TERR signals from those same devices. This is useful when several devices are “chained” together in a JTAG environment. PSD- soft Express puts TSTAT and TERR signals to open-drain by default. Click on 'Properties' in the JTAG-ISP window of PSDsoft Express to change to standard CMOS push-pull ...
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... Also, the supply power is considerably different if the Turbo bit is 0. The AC power component gives the PLD and Flash memory a mA/MHz specification. Figure 25 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. The fitter report of PSDsoft Express indicates the number of Product Terms (PTs) used for a given design ...
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... Electrostatic Discharge Voltage (Human Body model) ESD Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi-Z) ...
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DSM2190F4 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests ...
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Table 25. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input N Reset Input or Output P Port Signal Output Q Output Data R RD Input (read) S Chip Select ...
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... Only on V STBY CSI >V –0.3 V (Notes CC V < V < 0.45 < V < PLD_TURBO = Off MHz (Note ) PLD_TURBO = On MHz During Flash memory Write/ Erase Only Read Only MHz is valid at or below 0.2V –0.1. V IL1 CC IH1 Min. Typ. Max. 0. –0.5 0.8 0.8V V +0.5 ...
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Table 27. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input to CPLD Output t ER Disable CPLD Register Clear or t ARP Preset Delay ...
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DSM2190F4 Table 28. CPLD Macrocell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High ...
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Figure 29. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Figure 30. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 31. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Figure 32. Asynchronous Clock Mode ...
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DSM2190F4 Table 30. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL t NIB Input to Combinatorial Delay INO Note: 1. Inputs ...
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Table 31. Read Timing Symbol Parameter t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV Data Valid 8-Bit Bus RLQV t RD Data Hold Time RHQX t RD Pulse Width RLRH t ...
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... Note: 1. Any input used to select an internal PSM function. 2. Assuming data is stable before active write signal. 3. Assuming write is active before data becomes valid. 4. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory. Figure 35. Write Timing ADDRESS ...
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... Power On Reset Active Low Time NLNH–PO t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode. Figure 36. Reset (RESET) Timing V (min ...
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DSM2190F4 Table 35. ISC Timing Symbol t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low Time (except for PLD) ISCCL t Clock (TCK, PC1) Frequency ...
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PACKAGE MECHANICAL PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular, Package Outline M PLCC-B Note: Drawing is not to scale. PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data Symbol Typ ...
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DSM2190F4 Table 36. Assignments – PLCC52 Pin No. Pin Assignments 1 GND 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 15 V ...
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PQFP52 - 52 lead Plastic Quad Flatpack, Package Outline Ne N QFP Note: Drawing is not to scale. PQFP52 - 52 lead Plastic Quad Flatpack, Package Mechanical Data Symb. Typ 2. 13.20 D1 10.00 ...
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DSM2190F4 Table 37. Pin Assignments – PQFP52 Pin No. Pin Assignments 1 PD2 2 PD1 3 PD0 4 PC7 5 PC6 6 PC5 7 PC4 GND 10 PC3 11 PC2 12 PC1 13 PC0 14 PA7 15 ...
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... PART NUMBERING Table 38. Ordering Information Scheme Example: Device Type DSM21 = DSP System Memory for ADSP-21XX Family DSP Applicability 90 = Analog Devices ADSP-219X family Memory Density F4 = 2Mbit x 8 (256K Bytes) Operating Voltage (Vcc 3.3V ± 10% Access Time 15 = 150 ns Package K = 52-pin PLCC T = 52-pin PQFP ...
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DSM2190F4 REVISION HISTORY Table 39. Document Revision History Date Rev. 27-Aug-2001 1.0 Document written 06-Nov-2001 1.1 Document released 17-Dec-2001 1.2 PQFP52 package mechanical data updated 18-Sep-2002 1.3 JTAG Debug bus separated from JTAG ISP bus 60/61 Description of Revision ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...