DSM2180F3V-15K6 STMicroelectronics, DSM2180F3V-15K6 Datasheet
DSM2180F3V-15K6
Specifications of DSM2180F3V-15K6
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DSM2180F3V-15K6 Summary of contents
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... Zero-Power Technology – 25μ ■ Small Packaging – 52-pin PQFP or 52-pin PLCC – Packages are ECOPACK ■ Memory Speed software ...Free – 150 ns Rev 2.0 DSM2180F3V NOT FOR NEW DESIGN PQFP52 (T) PLCC52 (K) TM cable with PC =3.3V CC ® 1/63 ...
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... DSM2180F3V TABLE OF CONTENTS Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DSP Address/Data/Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programmable Logic (PLDs Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Security and NVM Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specifying Mem Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Runtime control register definition ...
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... Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: Reset (Reset) Timing Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 57 Table: Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table: PQFP52 - 52 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table: Pin Assignments – PQFP52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DSM2180F3V 3/63 ...
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... DSM2180F3V SUMMARY DESCRIPTION These are system memory devices for use with Digital Signal Processors from the popular Analog Devices ADSP-218X family. DSM means Digital signal processor System Memory. A DSM device brings in-system programmable Flash memory, programmable logic, and additional I/O to DSP systems ...
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... EMI levels, and power consumption. DSM memory and logic are “zero-power”, meaning they BUS I/O automatically go to standby between memory ac- cesses or logic input changes, producing low ac- tive and standby current consumption, which is ideal for battery powered products. DSM2180F3V 5/63 ...
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... A programmable security bit in the DSM protects its contents from unauthorized viewing and copy- ing. When set, the security bit will block access of programming devices (JTAG or others) to the DSM Flash memory and PLD configuration. The Table 1. DSM2180F3V DSP Memory System Devices ISP Flash Part Number Memory DSM2180F3V-15 128K Bytes Eight 16K Byte Sectors 16 macro cells Table 2 ...
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... Maximum erase cycles is 100K and data retention is 15 years minimum. Flash memory, as well as the entire DSM device may be programmed with the JTAG ISP interface with no DSP involvement. DSM2180F3V instead of DMS strobe, only the upper byte DMS TM ...
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... DSM2180F3V Figure 5. Block Diagram SECURITY LOCK DSP ADDR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 PC2 PC7 DSP CONTROL CNTL0 CNTL1 CNTL2 PD0 PD1 PD2 RST\ PIN FEEDBACK NODE FEEDBACK Programmable Logic (PLDs) The DSM family contains two PLDS that may op- tionally run in Turbo or Non-Turbo mode ...
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... PSDsoft Express This is typically used to protect DSP boot code from being corrupted by inadvertent writes to Flash memory from the DSP. Pin Assignments Pin assignment are shown for the 52-pin PLCC package in Figure 2, and the 52-pin PQFP pack- age in Figure 3. DSM2180F3V TM programming cable is JTAG 9/ ...
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... DSM2180F3V Table 3. Pin Description Pin Name Type ADIO0-15 In Sixteen address inputs from the DSP. CNTL0 In Active low write strobe input (WR) from the DSP CNTL1 In Active low read strobe input (RD) from the DSP. CNTL2 In Active low Byte Memory Select (BMS) signal from the DSP. ...
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... Port D may be used for DSP address inputs, it does not have to be pins PC2 and PC7. Pin PB0. This pin is shown as a chip select for an external peripheral device such as a 16450 or 16550 UART. Equivalently, any free pin on Ports may be used for this. DSM2180F3V 11/63 ...
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... DSM2180F3V Figure 6. Typical Connections 12/63 ...
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... DSP uses the Page Register inside the DSM device to page through 8 pages of 16K Bytes as shown in Figure 7. Since DSP Data accesses are by 16 bits, not 8 bits, the upper byte of a 16-bit DSP Data access must be ignored. DSM2180F3V signal is active. BMS 13/63 ...
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... DSM2180F3V Figure 7. Typical System Memory Map 14/63 ...
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... BMS the DSM Page Register outputs. This specification process is repeated for all other Flash memory segments, the csiop register block, and any exter- nal chip select signals (UART, etc.). , , or IOMS DMS DSM2180F3V . 15/63 ...
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... DSM2180F3V TM Figure 9. PSDsoft Express 16/63 Memory Mapping AI03779 ...
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... Read to determine if DSM devices Security Bit is active. C2 Logic 1 = device secured. No writes. Write to enable JTAG Pins (optional feature). Read to C7 check status. B0 Power Management Register 0. Write and read. B4 Power Management Register 2. Write and read. E0 Memory Page Register. Write and read. DSM2180F3V Description 17/63 ...
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... DSM2180F3V DETAILED OPERATION Figure 5 shows major functional areas of the de- vice: ■ Flash Memory ■ PLDs (DPLD, CPLD, Page Register) ■ DSP Bus Interface (Address, Data, Control) I/O Ports ■ ■ Runtime Control Registers ■ JTAG ISP Interface The following describes these functions in more detail ...
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... Write 55h Write 80h Write AAh to to XXAAAh to XX555h XX555h Write 55h Write 80h Write AAh to to XXAAAh to XX555h XX555h DSM2180F3V Cycle 5 Cycle 6 Cycle 7 Write 55h Write 10h to XXAAAh to XX555h Write 30h Write 30h Write 55h to another to another to XXAAAh ...
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... DSM2180F3V Instruction Sequences An instruction sequence consists of a sequence of specific write or read operations. Each byte written to the device is received and sequentially decoded and not executed as a standard write operation to the memory array. The instruction sequence is ex- ecuted when the correct number of bytes are prop- ...
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... DSP. Status may be checked using any of three methods: Data Poll- ing, Data Toggle, or Ready/Busy (pin PC3). Data Polling. Polling on the Data Polling Flag (DQ7) bit is a method of checking whether a Pro- DSM2180F3V 21/63 ...
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... DSM2180F3V gram or Erase cycle is in progress or has complet- ed. Figure 10 shows the Data Polling algorithm. When the DSP issues a Program instruction se- quence, the embedded algorithm within the device begins. The DSP then reads the location of the byte to be programmed in Flash memory to check status ...
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... Toggle Flag (DQ6) bit, and the Data Polling Flag (DQ7) bit, as detailed in the section entitled “Pro- gramming Flash Memory”, on page 21. During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instruction sequences. Erasure of one DSM2180F3V 23/63 ...
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... DSM2180F3V Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. The address provided with the initial Flash Sector Erase command sequence (Table 5) must select the first desired sector (FS0 - FS7) to erase. Sub- sequent sector erase commands that are append within the time-out period must be addressed to other desired segments (FS0 - FS7) ...
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... Note: 1. DSP address lines A16, A17, and others may enter the DSM device on any pin on ports See Figure 6 for recommended connections. 2. Additional DSP control signals may enter the DMS device on any pin on Ports See Figure 6 for recom- mended connections. DSM2180F3V INTERNAL SELECTS AND LOGIC DPLD AND ...
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... DSM2180F3V The DPLD performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and I/O ports. The DPLD can generates External Chip Select (ECS0-ECS2) signals on Port D. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic ...
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... JTAG Select signal (enables JTAG operations on Port C when multiplexing JTAG signals with general I/O signals) ■ 3 external chip select output signals for Port D pins, each with one product term. (16) (8) (8) (8) (16) (3) (3) (1) (1) DSM2180F3V 3 FS0 3 FS1 3 FS2 3 FS3 8 Flash Memory Sector Selects 3 FS4 3 FS5 ...
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... DSM2180F3V COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. See application note AN1171 for details on how to specify logic us- ing PSDsoft Express. As shown in Figure 15, the CPLD has the following blocks: ■ ...
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... TM , but ■ McellBC0-McellBC3 all have four native product terms and may borrow up to five more ■ McellBC4-McellBC7 all have four native product terms and may borrow up to six more. DSM2180F3V PORT B PINS PORT C PINS ...
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... DSM2180F3V Each Macrocell may only borrow product terms from certain other Macrocells. Product terms al- ready in use by one Macrocell are not available for another Macrocell. Product term allocation does not add any propagation delay to the logic equation requires more product terms than are available to it through product term allocation, then “ ...
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... CPLD. Each product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by equa- tions specified in PSDsoft Express. See Applica- tion note AN1171. DSM2180F3V DIRECTION REGISTER Port Driver PT ...
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... DSM2180F3V DSP Bus Interface The “no-glue logic” DSP Bus Interface allows di- rect connection. DSP address, data, and control signals connect directly to the DSM device. See Figure 6 for typical connections. DSP address, data and control signals are routed to Flash memory, I/O control (csiop), OMCs, and IMCs within the DMS ...
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... DSP through normal read/write bus cycles of the csiop registers listed in Table 4. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit register refers to Bit 0 of its DSM2180F3V TM , and Port D Yes No ...
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... DSM2180F3V port. The three Port Configuration Registers (PCR), are shown in Table 12. Default is logic 0. Table 12. Port Configuration Registers (PCR) Register Name Port Data In B,C,D Data Out B,C,D Direction B,C,D 1 B,C,D Drive Select Note: 1. See Table 16 for Drive Register bit definition. Data In Register. The DSP may read the Data In registers in the csiop block at any time to deter- mine the logic state of a Port pin ...
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... P D DATA ■ CPLD Input – Via the Input Macrocells (IMC). ■ Open Drain/Slew Rate – pins PB3-PB0 can be configured to fast slew rate, pins PB7-PB4 can be configured to Open Drain Mode. DSM2180F3V Bit 3 Bit 2 Bit 1 Slew Slew Rate Rate Open Open Drain ...
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... DSM2180F3V Figure 21. Port C Structure DATA OUT REG MCELLBC [ 7:0 ] READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 21): ■ MCU I/O Mode ■ CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. ■ ...
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... Direction Register. (See Figure 23.) External Chip Selects for Port D pins do not consume OMCs. External chip select outputs can also come from the CPLD if chip se- lect equations are specified in PSDsoft Express for Ports DSM2180F3V PORT D PIN ENABLE PRODUCT TERM (.OE) AI02889 37/63 ...
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... DSM2180F3V Figure 23. Port D External Chip Select Signals 38/63 ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 AI02890 ...
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... Not used, and should be set to zero. CLKIN (PD1) input to the PLD AND Array is passed onto PLDs. Every change of CLKIN (PD1) Powers-up the PLD when Turbo bit is 0. Not used, and should be set to zero. Not used, and should be set to zero. DSM2180F3V 39/63 ...
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... DSM2180F3V PLD Power Management The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By setting the bit to 1, the Turbo mode is off and the PLDs consume the specified stand-by current when the inputs are not switching for an extended time of 100 ns ...
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... Boundary Scan functions. The DSM uses the JTAG interface for ISP only. However, the DSM device can reside in a standard JTAG chain with other JTAG devices as it will remain in BYPASS mode while other devices perform Boundary Scan. DSM2180F3V t NLNH t NLNH-A t OPR Warm Reset , CNTL0) High CNTL0) ...
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... TSTAT and TERR can be configured as open- drain type signals with PSDsoft Express. This fa- cilitates a wired-OR connection of TSTAT signals from multiple DSM2180F3V devices and a wired- OR connection of TERR signals from those same devices. This is useful when several devices are “chained” together in a JTAG environment. PSD- soft Express puts TSTAT and TERR signals to open-drain by default ...
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... PLDs erased to logic 1. The DSM on all JTAG- Configuration Register bits are set to 0. The code, CC configuration, and PLD logic are loaded using the programming procedure. The four basic JTAG ISP signals (TCK, TMS, TDI, TDO) are ready for ISP function. DSM2180F3V 43/63 ...
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... DSM2180F3V AC/DC PARAMETERS These tables describe the AD and DC parameters of the device: ❏ DC Electrical Specification ❏ AC Timing Specification PLD Timing ■ – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing ■ DSP Timing – Read Timing – ...
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... JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi- DSM2180F3V Min. Max. Unit –65 125 °C 235 °C –0.6 7.0 V – ...
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... DSM2180F3V DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 22. Operating Conditions Symbol V Supply Voltage ...
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... Logic Level High V Valid X No Longer a Valid Logic Level Z Float PW Pulse Width INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM WILL BE CHANGING FROM MAY CHANGE FROM WILL BE CHANGING DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 DSM2180F3V 47/63 ...
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... DSM2180F3V Table 26. DC Characteristics Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage (Note IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO Program ...
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... CPLD Register Clear or t ARPW Preset Pulse Width t CPLD Array Delay ARD Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0. -15 Conditions Min Max Any Macrocell 29 DSM2180F3V Slew PT Turbo Unit 1 Aloc Off Rate Add 4 Add 20 Sub 6 ns Add 20 Sub 6 ns Add 20 Sub 6 ns ...
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... DSM2180F3V Table 28. CPLD Macrocell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time CH t Clock Low Time CL t Clock to Output Delay ...
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... INPUT REGISTER OUTPUT Figure 31. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Figure 32. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT tER tEA tARPW tARP tCHA tCLA tSA tHA tCOA DSM2180F3V AI02863 AI02864 AI02860 AI02859 51/63 ...
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... DSM2180F3V Table 30. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL t NIB Input to Combinatorial Delay INO Note: 1. Inputs from Port B, and C relative to register/latch clock from the PLD. ...
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... Note: 1. Any input used to select an internal DSM function. Figure 34. Read Timing ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD Conditions Min 1 (Note ) AVQV ADDRESS VALID DATA VALID t SLQV t RLQV t RHQX t RLRH DSM2180F3V -15 Turbo Unit Off Max 150 Add 20 ns 150 tRHQZ AI04908 53/63 ...
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... DSM2180F3V Table 32. Write Timing Symbol Parameter t Address Valid to Leading Edge of WR AVWL t CS Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH t WR Data Hold Time WHDX t WR Pulse Width WLWH t Trailing Edge Address Invalid WHAX1 t Trailing Edge DPLD Address Invalid ...
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... Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode. Figure 36. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Parameter 2 Conditions 1 t OPR DSM2180F3V Min. Typ. Max 2.2 14 1200 100,000 100 30 Min ...
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... DSM2180F3V Table 35. ISC Timing Symbol Parameter t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low Time (except for PLD) ISCCL t Clock (TCK, PC1) Frequency (PLD only) ISCCFP t Clock (TCK, PC1) High Time (PLD only) ...
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... PACKAGE MECHANICAL In order to meet environmental requirements, ST offers the DSM2180F3V in ECOPACK es. These packages have a Lead-free second-lev- el interconnect. The category of second-level interconnect is marked on the package and on the PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular D1 M PLCC-B Note: Drawing is not to scale. PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular Symbol Typ ...
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... DSM2180F3V e 1. Table 36. Assignments – PLCC52 Pin No. Pin Assignments 1 GND 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 (VSTBY) 19 PC1 20 PC0 21 PA7 22 PA6 23 PA5 24 PA4 25 PA3 26 GND 58/63 – – – – ...
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... DSM2180F3V inches Typ. Min. 0.079 0.077 0.009 0.004 0.520 0.510 0.394 0.390 0.307 – 0.520 0.510 0.394 ...
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... DSM2180F3V Table 37. Pin Assignments – PQFP52 Pin No. Pin Assignments 1 PD2 2 PD1 3 PD0 4 PC7 5 PC6 6 PC5 7 PC4 GND 10 PC3 11 PC2 12 PC1 13 PC0 14 PA7 15 PA6 16 PA5 17 PA4 18 PA3 19 GND 20 PA2 21 PA1 22 PA0 23 AD0 24 AD1 25 AD2 26 AD3 60/63 CC Pin No. Pin Assignments 27 AD4 28 AD5 29 AD6 ...
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... Temperature Range – (Industrial) Note: 1. The 5V±10% devices are not covered by this data sheet, but by the DSM2180F3 data sheet. For a list of available options (speed, package, etc.) or for further information on any aspect of this DSM21 device, please contact your nearest ST Sales Of- fice. DSM2180F3V 61/63 ...
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... DSM2180F3V REVISION HISTORY Table 39. Document Revision History Date Rev. 06-Nov-2001 1.0 Document for the 3.3V±10% range separated out from the data sheet on the 5V±10% range 17-Dec-2001 1.1 PQFP52 package mechanical data updated Disclaimer updated. Updated datasheet status to “not for new design”. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com DSM2180F3V 63/63 ...