ISL9208IRZ-T Intersil, ISL9208IRZ-T Datasheet - Page 21

• Manufacturer Part Number: ISL9208IRZ-T
• Description: IC MULTI-CELL LI-ION PROT 32-QFN
• Manufacturer: Intersil

Specifications of ISL9208IRZ-T

• Function: Battery Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 5 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cell Balancing
OVERVIEW
A typical ISL9208 Li-ion battery pack consists of five to
seven cells in series, with one or more cells in parallel. This
combination gives both the voltage and power necessary for
power tool, e-bikes, electric wheel chairs, portable medical
equipment, and battery powered industrial applications.
While the series/parallel combination of Li-ion cells is
common, the configuration is not as efficient as it could be,
because any capacity mismatch between series-connected
cells reduces the overall pack capacity. This mismatch is
greater as the number of series cells and the load current
increase. Cell balancing techniques increase the capacity,
and the operating time, of Li-ion battery packs.
DEFINITION OF CELL BALANCING
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a
series string. Normally, of course, cells in a series string
receive identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL9208 devices, the only external components required are
balancing resistors.
CELL BALANCE OPERATION
Cell balancing is accomplished through a microcontroller
algorithm. This algorithm compares the cell voltages (a
representation of the pack capacity) and turns on balancing
for the cells that have the higher voltages. There are many
parameters that should be considered when writing this
algorithm. An example cell balancing algorithm is available
in the ISL9208EVAL1Z evaluation kit.
The microcontroller turns on the specific cell balancing by
setting a bit in the Cell Balance Register. Each bit in the
register corresponds to one cell’s balancing control. When
the bit is set, an internal cell balancing FET turns on. This
shorts an external resistor across the specified cell. The
maximum current that can be drawn from (or bypassed
around) the cell is 200mA. This current is set by selecting
the value of the external resistor. Figure 7 shows an example
with a 200mA (maximum) balancing current.
With lower balancing current, more balancing FETs can be
turned on at once, without exceeding the device power
dissipation limits or generating excessive balancing current
that will heat the external resistor.
External VMON/CFET Protection Mechanisms
When there is a single charge/discharge path, a blocking
diode is recommended in the VMON to P- path in ISL9208
solution. See D1 in Figure 8. This diode is to protect against
a negative voltage on the VMON pin that can occur when the
FETs are off and the charger connects to the pack. This
diode is not needed when there is a separate charge and
discharge path, because the voltages on P- (discharge) are
likely always positive. The diode also is not needed if the
21
ISL9208
differential between the minimum pack voltage and
maximum charger voltage does not exceed 22V.
When the pack is designed with a single set of
charge/discharge FETs, the ISL9208 CFET pin should be
protected in the event of an over-current or short circuit
shutdown. When this happens, the FET opens suddenly.
The flyback voltage from the motor windings could exceed
the maximum input voltage on the CFET pin. So, it is
recommended that an additional external series diode be
placed between the CFET pin of the ISL9208 and the gate of
the Charge FET. See Diode D3 in Figure 8. This will reduce
the CFET gate voltage, but not significantly.
Finally, to protect the Charge FET itself in the event of a
large negative voltage on the Pack- pin, zener diode D4 is
added. The large negative voltage can occur when the P- pin
goes significantly negative, while the CFET pin is being
internally clamped at VSS. The zener voltage of D4 should
be less than the V
FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH
FIGURE 8. USE OF A DIODES FOR PROTECTING THE CFET
200mA
200mA BALANCING CURRENT
AND VMON PINS
1W
1W
ISL9208
21Ω
21Ω
VMON
GS
CFET
DFET
(max) specification of the FET.
VCELL1
VSS
CB1
VC7/VCC
CB7
D
3
D
ISL9208
7 6 5 4 3 2 1
10M
1
1M
D
4
November 2, 2007
(REG 02H)
CELL
BALANCE
CONTROL
PACK+
PACK-
FN6446.1