ISL6296DH-T Intersil, ISL6296DH-T Datasheet
ISL6296DH-T
Specifications of ISL6296DH-T
Related parts for ISL6296DH-T
ISL6296DH-T Summary of contents
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... TIO ” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. ISL6296 FN9201.2 | Intersil (and design registered trademark of Intersil Americas Inc. ...
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... PART (Note 1) MARKING ISL6296DHZ-T 296Z ISL6296DRZ-T 96Z ISL6296DH-T 296D ISL6296EVAL1 ISL6296 Evaluation Kit * Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... Thermal Resistance (Typical) SOT-23 Package (Note 2x3 TDFN Package (Notes Maximum Junction Temperature (Plastic Package +125°C Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -25°C to +85° SYMBOL TEST CONDITIONS V During normal operation ...
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Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: T PARAMETER XSD Input Deglitch Time Device Wake-Up Time Device Sleep Wait Time Auto-Sleep Time-Out Period OTP ROM ...
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Typical Applications PACK+ XSD PACK- FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE BATTERY PACK+ XSD PACK- FIGURE 2. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE XSD BUS Block Diagram XSD 5 ISL6296 ...
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Theory of Operation The ISL6296 contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage 96-Bit of secret for the ...
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OTP ROM The 16-Byte OTP ROM memory is based on EEPROM technology and is incorporated into the ISL6296 for storage of non-volatile information. OTP ROM contents (refer to Table 8) can include but not limited to: 1) Device default settings ...
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Secret 64-bit Secret 32-bit Hash Function 32-bit Hash Function FlexiHash FlexiHash Engine Engine 32-bit Hash Seed 32-bit Hash Seed FIGURE 4. AUTHENTICATION PROCESS FLOW DIAGRAM It is recommended that device authentication be done once in a while to maximize ...
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8-bit CRC Calculator 8-bit CRC Calculator 8-bit CRC Calculator MA[7:6] MA[7:6] MA[7:6] Polynom = Polynom = Polynom = ...
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... XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication ...
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HOST Open-Drain Port Pin TX RX FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS XSD TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER SYM Bit Time 0. ...
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BYTES BYTES BYTES FIGURE 9. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION OPCODE DESCRIPTION 00 Write Operation 01 Read Operation (normal) 10 Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the ...
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Bus Transaction Protocol The XSD bus for the ISL6296 defines three types of bus transactions. Figure 10 shows the bus transaction protocol. The blue color represents the signal sent by the host and the green color stands for the signal ...
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... Table 10 describes DD the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only, and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error. ...
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TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1) ADDRESS NAME DESCRIPTION 1-00 MSCR Master Control 1-01 STAT Device Status ADDRESS NAME DESCRIPTION 2-00 SESL Secrets Selection 2-01 CHLG Challenge Code Register 2-05 AUTH Authentication Code Register TABLE 11. DEFAULT CONFIGURATION ...
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ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET SET #2 (SE2A/B/C/D) These address locations store the second set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[1] bit at OTP ROM location ...
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... One way is to use a spare Universal Asynchronous Receiver/Transmitter (UART). A general purpose input/output (GPIO) can be used if no UART is available for the XSD communication. Refer to application note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor. Pull-Up Resistor Selection ...
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Small Outline Transistor Plastic Packages (SOT23- 0.20 (0.008 0.10 (0.004 WITH PLATING b1 c BASE METAL ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...