ISL6296DH-T Intersil, ISL6296DH-T Datasheet - Page 12

• Manufacturer Part Number: ISL6296DH-T
• Description: IC BATT AUTHENTICATION SOT-23
• Manufacturer: Intersil
• Series: FlexiHash™r

Specifications of ISL6296DH-T

• Function: Battery Authentication
• Battery Type: Li-Ion, Li-Pol, NiMH
• Voltage - Supply: 2.6 V ~ 4.8 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SC-74A, SOT-753
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Access Instruction Frame
The XSD access instruction frame is shown in Figure 9. The
instruction frame consists of 16 bits of digital signal with the
contents described as follows.
CS FIELD
The CS field is a 1-Bit Chip Address Selection. An initial 1-bit
Chip Address code of ‘0’ is pre-programmed into the
device’s OTP ROM address location 0-00[7:6] at the time of
chip manufacture, and may be re-programmed by the pack
manufacturer if needed. If the CS code in the instruction
does not match the device’s Chip Address code, the
instruction, and any subsequent frames that follow, will be
ignored until a break command is received.
OPCODE FIELD
The OPCODE is a 2-bit field defines the operation of the
transaction following the instruction frame. The operations
are described in Table 4.
BANK FIELD
The memories in the ISL6296 are divided into four banks.
The BANK field is defined in Table 5.
OPCODE
BYTES
FIELD
5 to 6
00
01
10
11
0
1
2
3
4
7
DATA BYTES
TO FOLLOW
Write Operation
Read Operation (normal)
Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame.
Sleep Mode Activation
N/A
N/A
16
DESCRIPTION
0
1
2
4
15
15
15
BYTES
BYTES
BYTES
OTP ROM
WRITE
12
X
FIGURE 9. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION
OTP ROM
Write to device register
Read from device register
Immediately sets the device in Sleep mode.
Note: After detecting the ‘11’ Opcode, the device immediately enters sleep mode. If more than 3
bits sent, subsequent pulses may wake the device up again.
READ
X
X
X
TABLE 4. DEFINITION OF THE OPCODE FIELD
TABLE 6. DEFINITION OF THE BYTES FIELD
ADDRESS
ADDRESS
ADDRESS
REG READ
OR WRITE
X
X
ISL6296
CHLG CODE
WRITE
X
ADDRESS FIELD
The address field indicates the starting address of a memory
or register read or write sequence. Keep in mind that only odd
starting addresses are allowed for the OTP ROM access.
BYTES FIELD
The bytes field indicates the number of data bytes to read or
write, not including the CRC byte. Not all BYTES Field
settings are supported. Only settings marked with an ‘X’ is
valid for a particular bus instruction, as indicated in Table 6.
Attempt to read or write with an invalid BYTES setting may
yield unpredictable results.
Writing to OTP ROM can occur at only two bytes at a time,
but reading from OTP ROM can happen at 2, 4 or 16 bytes
at a time. Writing to and reading from OTP ROM in any other
byte denomination will yield unpredictable result, and should
therefore be strictly prohibited.
BANK
BANK
BANK
BANK
00
01
10
11
Invalid selection. Causes a bus error.
Must use 1-byte read for clearing of the STAT register.
Invalid selection. Causes a bus error.
Invalid selection. Causes a bus error.
For reading from OTP ROM only (prior to lock-out).
OTP ROM
Control and Status Registers
Device Authentication Registers
Test Registers (Reserved)
ACTION
OPCODE
OPCODE
OPCODE
TABLE 5. BANK FIELD DEFINITION.
MEMORY/REGISTER BANK SELECTION
CS
CS
CS
0
0
0
COMMENTS
March 21, 2008
FN9201.2