PCA9625D/S911,518 NXP Semiconductors, PCA9625D/S911,518 Datasheet
PCA9625D/S911,518
Specifications of PCA9625D/S911,518
PCA9625D/S911-T
PCA9625D/S911-T
Related parts for PCA9625D/S911,518
PCA9625D/S911,518 Summary of contents
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PCA9625 16-bit Fm+ I Rev. 02 — 15 January 2008 1. General description The PCA9625 dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM ...
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... NXP Semiconductors 2. Features I 16 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off ...
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... NXP Semiconductors 3. Applications I RGB or RGBA LED drivers I LED status information I LED displays I LCD backlights I Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9625D PCA9625D PCA9625_2 Product data sheet Package Name Description SO32 plastic small outline package; 32 leads; body width 7.5 mm Rev. 02 — ...
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A0 PCA9625 SCL INPUT FILTER SDA POWER- RESET V SS PWM REGISTER X BRIGHTNESS CONTROL 24.3 kHz 97 kHz GRPFREQ REGISTER 25 MHz OSCILLATOR 190 Hz OE Remark: Only one LED output shown for clarity. Fig 1. Block ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol LED13 LED14 LED15 SCL SDA LED0 LED1 LED2 LED3 PCA9625_2 Product data sheet 1 LED13 LED14 2 LED15 SCL 7 8 SDA PCA9625D LED0 LED1 16 Pin configuration for SO32 Pin description for SO32 ...
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... NXP Semiconductors Table 2. Symbol V SS(DRV)FET LED4 LED5 LED6 LED7 V DD(DRV)FET DD(DRV)FET LED8 LED9 LED10 LED11 V SS(DRV)FET LED12 7. Functional description Refer to 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. There are a maximum of 128 possible programmable addresses using the 7 hardware address pins ...
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... NXP Semiconductors Fig 3. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED All Call I • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I • ...
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... NXP Semiconductors Fig 4. Remark: The Software Reset regular I 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9625, which will be stored in the Control register. The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment fl ...
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... NXP Semiconductors AI[2:0] = 000 is used when the same register must be accessed several times during a single I is overwritten each time the register is accessed during a write operation. AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming. AI[2:0] = 101 is used when the 16 LED drivers must be individually programmed with different values during the same I setting to another color setting ...
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... NXP Semiconductors [1][2] Table 4. Register summary Register number (hex [1] Only D[4: 0000 to 1 1011 are allowed and will be acknowledged. D[4: 1100 to 1 1111 are reserved and will not be acknowledged. [2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation. ...
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... NXP Semiconductors 7.3.2 Mode register 2, MODE2 Table 6. Legend: * default value. Bit [1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9625. Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only. 7.3.3 PWM0 to PWM15, individual brightness control Table 7. Legend: * default value. ...
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... NXP Semiconductors A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = (LEDOUT0 to LEDOUT3 registers). ...
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... NXP Semiconductors 7.3.6 LEDOUT0 to LEDOUT3, LED driver output state Table 10. Legend: * default value. Address 14h 15h 16h 17h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — ...
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... NXP Semiconductors Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses (MODE1 register). Only the 7 MSBs representing the I register is a read-only bit (0). When SUBx is set to logic 1, the corresponding I either ...
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... NXP Semiconductors 7.5 Power-on reset When power is applied to V condition until V PCA9625 registers and I zeroes) causing all the channels to be deselected. Thereafter reset the device. 7.6 Software Reset The Software Reset Call (SWRST Call) allows all the devices in the I the power-up state value through a specific formatted I correctly, it implies that the I bus ...
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... NXP Semiconductors 7.7 Individual brightness control with group dimming/blinking A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs): • ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 11. Write to a specific register slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave Fig 12. Write to all registers using the Auto-Increment feature ...
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... NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP from master condition Fig 14. Read all registers using the Auto-Increment feature slave address sequence (A) ...
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... NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE (1) OE requires pull-up resistor if control signal from the master is open-drain C-bus address = 0010 101x. Fig 16. Typical application PCA9625_2 Product data sheet ( DD(DRV)FET SDA LED0 SCL LED1 LED2 OE LED3 PCA9625 LED4 ...
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... NXP Semiconductors 11. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V voltage on an input/output pin I/O V LED driver voltage drv(LED) V FET driver supply voltage DD(DRV)FET I output current on pin LEDn O(LEDn) I ground supply current ...
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... NXP Semiconductors 13. Static characteristics Table 15. Static characteristics Symbol Parameter Supply V FET driver supply voltage DD(DRV)FET V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors Table 15. Static characteristics Symbol Parameter Address inputs V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i [1] V must be lowered to 0 order to reset part. DD [2] V and V voltages are independent, but V DD(DRV)FET drv(LED) [3] Each bit must be limited to a maximum of 100 mA and the total package limited to 1600 mA due to internal busing limits. ...
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... NXP Semiconductors [4] The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t f 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t ...
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... NXP Semiconductors 15. Test information Fig 19. Test circuitry for switching times PCA9625_2 Product data sheet V I PULSE GENERATOR R = Load resistor for LEDn. R for SDA and SCL > less current Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z T Rev. 02 — ...
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... NXP Semiconductors 16. Package outline SO32: plastic small outline package; 32 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 17. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 19. Acronym CDM DUT ESD FET HBM 2 I C-bus LED LSB MM MSB NMOS ...
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... NXP Semiconductors 20. Revision history Table 20. Revision history Document ID Release date PCA9625_2 20080115 • Modifications: Section 2 • Section 7.2 “Control when the four LED drivers ...” to “AI[2:0] = 101 is used when the 16 LED drivers ...” • Table 6 “MODE2 - Mode register 2 (address 01h) bit re-written • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 6 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 6 2 7.1.2 LED All Call I C-bus address . . . . . . . . . . . . . . ...