L6569D STMicroelectronics, L6569D Datasheet - Page 5

• Manufacturer Part Number: L6569D
• Description: IC DRVR HALF BRDG HV W/OSC 8SOIC
• Manufacturer: STMicroelectronics
• Type: High Voltage Half Bridger

Specifications of L6569D

• Configuration: Half Bridge
• Input Type: Self Oscillating
• Current - Peak: 175mA
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 10 V ~ 16.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Supply Voltage (min): 10 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• For Use With: 497-6409 - BOARD EVAL BIPO SOLUTION FOR PFC497-4738 - BOARD EVAL LIGHTING L6569
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-5796-5

Bootstrap Function
The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in sim-
ilar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the
Upper External Mosfet.
The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven
by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side
Gate driver (LVG pin), actually working as a synchronous rectifier .
The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG
High) for a time interval:
starting from the time the Supply Voltage V
After time T
(typical value).
In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is
drive OFF until V
Being the LDMOS used to implement the bootstrap operation a "bi-directional" switch the current flowing into
the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING opera-
tions is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example,
when the load is removed and an high resistive value is placed in series with the gate of the external Power
Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided
(fig. 7).
Let's consider the steps that should be taken.
1) Calculate the Turn on delay ( td ) of your Lower Power MOS:
2) Calculate the Fall time ( tf ) of your Lower Power MOS:
where:
R
R
V
V
3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS
(remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example
is given where:
V
V
The V
tion.
TH
S
S
HV
g
id
= External gate resistor
= Low Voltage Supply.
= Low Voltage Supply
= 50 , typical equivalent output resistance of the driving buffer (when sourcing current)
, C
= High Voltage Supply Rail
BOOT
iss
and Q
1
voltage swing must fall below the curve identified by the actual operating frequency of your applica-
(see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a R
gd
S
has reached the Turn On Threshold (V
are Power MOS parameters
t
d
T
=
C
= R
R
S
t
g
has reached the Turn On Voltage (V
F
f
+
· C
=
R
----------------------- - Q
V
F
R
id
S
· In2
g
–
+
C
V
R
SUVPp
iss
T H
i d
1.1 · R
ln
), then again the T
gd
------------------- -
1
F
–
1
· C
V
---------- -
V
TH
S
F
C
SUVP
time interval starts as above.
= 9 V typical value).
L6569 L6569A
ON
=120
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