ISL6622IBZ Intersil, ISL6622IBZ Datasheet - Page 7

• Manufacturer Part Number: ISL6622IBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6622IBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Gate Voltage Optimization Technology (GVOT)
The ISL6622 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. During light
load operation, the switching losses dominate system
performance. Dropping down to a lower drive voltage with
GVOT during light load operation can reduce the switching
losses and maximize system efficiency.
Figure 2 shows that the gate drive voltage optimization is
accomplished via an internal low drop out regulator (LDO)
that regulates the lower gate drive voltage. LVCC is driven to
a lower voltage depending on the state of the internal PSI
signal and the GD_SEL pin impedance. The input and
output of this internal regulator is the VCC and LVCC pins,
respectively. Both VCC and LVCC should be decoupled with
a high quality low ESR ceramic capacitor.
In the 8 Ld SOIC package, the ISL6622 drives the upper and
lower gates close to VCC during normal PWM mode, while
the lower gate drops down to a fixed 5.75V during PSI mode.
The 10 Ld DFN part offers more flexibility: the upper gate can
be driven from 5V to 12V via the UVCC pin, while the lower
gate has a resistor-selectable drive voltage of 5.75V, 6.75V,
and 7.75V during PSI mode. This provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses. Table 1 shows
the LDO output (LVCC) level set by the PWM input and
GD_SEL pin impedance.
EXTERNAL CIRCUIT
FIGURE 2. GATE VOLTAGE OPTIMIZATION (GVOT) DETAIL
VIN
RCC = OPTION FOR HIGHER LVCC
PWM INPUT
5V
5V
0V
0V
RCC
>
THAN PRE-SET BY GD_SEL
TABLE 1. LDO OPERATION AND OPTIONS
2.5V
LVCC
VCC
1µF
1µF
Floating
4.5kΩ to GND
GND
DON’T CARE
GD_SEL PIN
ISL6622 INTERNAL CIRCUIT
7
GVOT
LDO
5.75V (Typical; Fixed in
SOIC Package)
6.75V (Typical)
7.75V (Typical)
11.20V (Typical)
LVCC @ 50mA DC LOAD
+
-
PSI AND
SET BY
GD_SEL
DRIVER
+
LGATE
-
ISL6622
Figure 3 illustrates the internal LDO’s variation with the
average load current plotted over a range of temperatures
spanning from -40
LVCC voltage be necessary, a resistor (R
shunt the LDO, as shown in Figure 2. The resistor delivers
part of the LGATE drive current, leaving less current going
through the internal LDO, elevating the LDO’s output
voltage. Further reduction in RCC’s value can raise the
LVCC voltage further, as desired.
Figure 4 also details the typical LDO performance when the
pass element is fully enhanced, as it is the case when the
driver operates in CCM.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds rising POR threshold,
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the POR
falling threshold, operation of the driver is disabled.
FIGURE 3. TYPICAL LVCC VARIATION WITH LOAD (CCM)
FIGURE 4. TYPICAL LVCC VARIATION WITH LOAD (DEM)
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
0
0
GD_SEL 4.5kΩ TO GND
GD_SEL TIED TO GND
GD_SEL FLOATING
20
20
°
C to +120
AVERAGE LOAD CURRENT (mA)
AVERAGE LOAD CURRENT (mA)
40
40
°
C. Should finer tweaking of this
+40°C
+40°C
60
60
+40°C
+120°C -40°C
+120°C
+120°C
CC
) can be used to
VCC = 12V
+40°C
80
80
-40°C
October 30, 2008
-40°C
FN6470.2
100
100