LP3971SQ-2G16/NOPB National Semiconductor, LP3971SQ-2G16/NOPB Datasheet - Page 19

• Manufacturer Part Number: LP3971SQ-2G16/NOPB
• Description: IC PMU FOR APPL PROCESSORS 40LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3971SQ-2G16/NOPB

• Applications: Processor
• Current - Supply: 60µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP3971SQ-2G16; LP3971SQ-2G16; LP3971SQ-2G16TR

V
V
V
I
F
t
t
t
t
t
t
t
T
T
OL
BF
HOLD
CLKLP
CLKHP
SU
DATAHLD
CLKSU
Symbol
CLK
SU
TRANS
IL
IH
OL
I
Unless otherwise noted, V
boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes 2, 6) and (Note 9)
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ
following equation: TA-MAX = TJ-MAX-OP – (θ
Note 4: Junction-to-ambient thermal resistance (θ
JEDEC standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane
on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°
C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum
power dissipation exists, special care must be paid to thermal dissipation issues in board design. The value of θ
on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high V
paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power
Efficiency and Power Dissipation section of this datasheet.
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200
pF capacitor discharged directly into each pin. (EAIJ)
Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production
tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 7: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
Note 8: Back-up battery charge current is programmable via the I
Note 9: The I
Note 10: LDO_RTC voltage can track LDO1 voltage. LP3971 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track LDO1 voltage
within 200mV down to 2.8V when LDO1 is enabled
Note 11: V
input operating voltage.
Note 12: The input voltage range recommended for ideal applications performance for the specified output voltages is given below:
V
V
Note 13: Test condition: for V
Note 14: This electrical specification is guaranteed by design.
Note 15: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 16: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
2
IN
IN
C Compatible Serial Interface Electrical Specifications (SDA and SCL)
= 2.7V to 5.5V for 0.80V < V
= (V
OUT
IN
+ 1V) to 5.5V for 1.8V
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
Low Level Output Current
Clock Frequency
Bus-Free Time Between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
CLK High Period
Set Up Time Repeated Start Condition
Data Hold Time
Data Set Up Time
Set Up Time for Start Condition
Maximum Pulse Width of Spikes that Must
be Suppressed by the Input Filter of Both
DATA & CLK Signals
minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages below the minimum
2
C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ range.
OUT
Parameter
OUT
IN
less than 2.7V, V
≤
= 3.6V. Typical values and limits appearing in normal type apply for T
< 1.8V
V
OUT
≤
3.3V
JA
x PD-MAX).
JA
IN
) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
= 3.6V; for V
(Note 14)
(Note 14)
(Note 14)
V
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
2
OUT
C compatible interface. Refer to the Application Section for more information.
OL
greater than or equal to 2.7V, V
= 0.4V (Note 14)
Conditions
19
IN
= V
0.7 V
OUT
−0.5
Min
100
JA
3.0
1.3
0.6
1.3
0.6
0.6
0.6
+ 1V.
0
0
of this product can vary significantly, depending
RTC
J
= 25°C. Limits appearing in
Typ
IN
50
, high I
OUT
0.3 V
0.2 V
), special care must be
V
Max
400
RTC
JA
), as given by the
RTC
TRC
www.national.com
Units
kHz
mA
μs
μs
μs
μs
μs
μs
ns
μs
ns
V