LP3971SQ-2G16/NOPB National Semiconductor, LP3971SQ-2G16/NOPB Datasheet - Page 40

• Manufacturer Part Number: LP3971SQ-2G16/NOPB
• Description: IC PMU FOR APPL PROCESSORS 40LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3971SQ-2G16/NOPB

• Applications: Processor
• Current - Supply: 60µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP3971SQ-2G16; LP3971SQ-2G16; LP3971SQ-2G16TR

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SYS_EN
PWR_EN
SCL
SDA
nRSTI
nRSTO
nBATT_FLT
PWR_ON
nTEST_JIG
SPARE
EXT_WAKEUP
GPIO1/nCHG_EN
GPIO2
DIGITAL INTERFACE CONTROL SIGNALS
*User assignable via Bit4 8h'0E
POWER DOMAIN ENABLES
LDO_RTC TRACKING (nIO_TRACK)
LP3971 has a tracking function (nIO_TRACK). When en-
abled, LDO_RTC voltage will track LDO1 voltage within 200
mV down to 2.8V when LDO1 is enabled. This function can
be switched on/off by BPTR (8h'0E) register bit.
LDO4, LDO5 AND BUCK 2 ENABLE SELECTION
(LDO4_ESEL, LDO5_ESEL AND BUCK2_ESEL)
LDO4, 5 and BUCK2 power domain enable is possible to
change between SYS_EN and PWR_EN by register bits.
WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG,
SPARE AND EXT_WAKEUP)
Three input pins can be used to assert wakeup output for 10
ms for application processor notification to wakeup. SPARE
Input can be programmed through I
be active low or high (SPARE bit, Default is active low ‘1’). A
reason for wakeup event can be read through I
interface also. Additionally wakeup inputs have 30 ms de-
bounce filtering. Furthermore PWR_ON have distinguishing
between short and long (
Signal
PMU Output
LDO_RTC
BUCK1
BUCK2
BUCK3
LDO1
LDO2
LDO3
LDO4
LDO5
High Voltage Power Enable
Low Voltage Power Enable
Serial Bus Clock Line
Serial Bus Data Line
Forces an Unconditional Hardware Reset
Forces an Unconditional Hardware Reset
Main Battery Removed or Discharged Indicator
Wakeup Input to CPU
Wakeup Input to CPU
Wakeup Input to CPU
Wake-Up Output for Application Processor
General Purpose I/O/External Back-Up Battery Charger
General Purpose I/O
∼
1s) pulses (push button input).
2
C compatible interface to
2
C compatible
Definition
PWR_EN/SYS_EN
PWR_EN/SYS_EN
SYS_EN/PWR_EN
HW Enable
PWR_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
40
-
LP3971 also has an internal Thermal Shutdown early warning
that generates a wakeup to the system also. This is generated
usually at 125°C.
Active State
High/Low*
Clock
-/Low
High
High
High
High
Low
Low
Low
Low
-
SW Enable
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
LDO5_EN
B1_EN
B2_EN
B3_EN
-
Bidirectional/Input
Signal Direction
Bidirectional
Bidirectional
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
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