LP3971SQ-2G16/NOPB National Semiconductor, LP3971SQ-2G16/NOPB Datasheet - Page 44

IC PMU FOR APPL PROCESSORS 40LLP

LP3971SQ-2G16/NOPB

Manufacturer Part Number
LP3971SQ-2G16/NOPB
Description
IC PMU FOR APPL PROCESSORS 40LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of LP3971SQ-2G16/NOPB

Applications
Processor
Current - Supply
60µA
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-LLP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LP3971SQ-2G16
LP3971SQ-2G16
LP3971SQ-2G16TR
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POWER-ON TIMING
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted
(low). Upon assertion of nRST the processor enters hardware
reset state. The LP3971 holds the nRST low long enough (50
ms typ.) to allow the processor time to initiate the reset state.
RESET SEQUENCE
1.
2.
3.
4.
5.
Symbol
t1
t2
t3
t4
t5
nRSTI is asserted.
nRSTO is asserted and will de-asserts after a minimum
of 50 mS
The Applications processor waits for the de-assertion of
nBATT_FLT to indicate system power (V
After system power (V
asserts nBATT_FLT.
The Applications processor asserts SYS_EN, the
LP3971 enables the system high-voltage power
Description
Delay from V
Delay from nBATT_FLT de-assertion to nRSTI assertion
Delay from nRST de-assertion to SYS_EN assertion
Delay from SYS_EN assertion to PWR_EN assertion
Delay from PWR_EN assertion to nRSTO de-assertion
IN
CC
) is turned on, the LP3971 de-
_RTC assertion to nRSTO de-assertion
IN
) is available.
44
6.
7.
8.
9.
10. The Applications processor begins the execution of
supplies. The Applications processor starts its
countdown timer.
The LP3971 enables the high-voltage power supplies.
Countdown timer expires; the Applications processor
asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
The Applications processor asserts PWR_EN, the
LP3971 enables the low-voltage regulators.
Countdown timer expires; If enabled power domains are
OK (I
enabling the processors 13 MHz oscillator and PLL’s.
code.
2
C read) the power up sequence continues by
Min
50
Typ
100
125
125
10
Max
Units
mS
mS
mS
mS
µS

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