ISL6308CRZ Intersil, ISL6308CRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6308CRZ
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

through the upper MOSFET across V
dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
When designing the ISL6308 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
P
P
I
P
DR
P
P
Qg_TOT
Qg_TOT
UP 3 ,
UP 4 ,
Qg_Q1
Qg_Q2
=
≈
=
⎛
⎝
3
-- - Q
2
r
DS ON
V
, due to the gate charge of MOSFETs and the
•
=
=
=
IN
(
3
-- - Q
2
Q
P
G1
⋅
Qg_Q1
G2
⋅
Q
)
rr
•
⋅
G1
⋅
N
d
UP,4
⋅
PVCC F
F
Q1
⋅
⋅
SW
+
PVCC F
⎛
⎜
⎝
P
+
.
I
----- -
N
M
Qg_Q2
Q
⎞
⎟
⎠
⋅
G2
2
UP,3
+
SW
⋅
•
I
--------- -
PP
12
19
SW
N
+
⋅
.
2
Q2
N
I
Q
Q2
⋅
⎞
⎠
⋅
N
VCC
•
Q1
⋅
N
N
IN
PHASE
PHASE
⋅
N
. The power
PHASE
•
F
SW
+
(EQ. 20)
I
(EQ. 21)
(EQ. 18)
(EQ. 19)
Q
ISL6308
In Equations 20 and 21, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
phase, respectively; N
phases. The I
controller without capacitive load and is typically 75mW at
300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
power will be dissipated by the external gate resistors (R
and R
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
DR_UP
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
PVCC
Q2
G2
, and in the boot strap diode, P
) and the internal gate resistors (R
PHASE
are the number of upper and lower MOSFETs per
R
R
LO2
BOOT
HI2
R
Q*
R
LO1
HI1
VCC product is the quiescent power of the
Qg_Q2
DR_UP
LGATE
PHASE
UGATE
G1
is the total lower gate drive power
, the lower drive path resistance,
Qg_Q1
and Q
is the number of active
R
G2
is the total upper gate drive
R
G2
G
G1
G
) is defined at the
R
C
Q
GI2
GD
BOOT
R
C
C
is the driver total
GI1
GD
GS
C
GS
GI1
. The rest of the
S
September 30, 2008
S
and R
D
D
Q2
C
GI2
FN9208.4
DS
Q1
Q1
C
DS
) of
G1