ISL6308CRZ Intersil, ISL6308CRZ Datasheet - Page 24

• Manufacturer Part Number: ISL6308CRZ
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI, the load-current slew rate, di/dt, and the
maximum allowable output-voltage deviation under transient
loading, ΔV
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as follows:
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
ΔV
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
≈
0
(
ESL
LOG
20
log
)
MAX
⋅
⎛
⎝
di
---- -
dt
R2
------- -
R1
+
⎞
⎠
. Capacitors are characterized according to
MAX
(
ESR
F
Z1
.
F
F
) ΔI
LC
Z2
⋅
F
F
24
CE
P1
F
0
F
20
P2
log
G
CL
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
CLOSED LOOP GAIN
MAX V
G
V OSC
MOD
MODULATOR GAIN
FREQUENCY
⋅
IN
G
(EQ. 39)
FB
ISL6308
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 9 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 41 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 18, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 24. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
L
L
L
≤
≤
≥
MAX
2 N C V
---------------------------------
(
--------------------------------- -
(
1.25
ESR
⋅
(
(
. This places an upper limit on inductance.
ΔI
ΔI
⋅
) N C
)
⋅
)
PP(MAX)
)
⋅
2
2
⋅
⎛
⎝
------------------------------------------------------------------- -
⋅
V
F
O
IN
SW
⋅
⋅
–
ΔV
ΔV
N V
⋅
, determines the lower limit on the
V
MAX
⋅
MAX
IN
OUT
⋅
V
C,PP
–
–
PP MAX
(
(
⎞ V
⎠
ΔI ESR
ΔI ESR
(
⋅
(ESR). Thus, once the output
⋅
⋅
OUT
)
)
)
⋅
⎛
⎝
V
IN
–
V
O
September 30, 2008
⎞
⎠
(EQ. 42)
(EQ. 41)
(EQ. 40)
FN9208.4