ISL6521CBZ-T Intersil, ISL6521CBZ-T Datasheet - Page 11

• Manufacturer Part Number: ISL6521CBZ-T
• Description: IC CTRLR PWM BUCK DC/DC 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6521CBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 325kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 325kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Transistors Selection/Considerations
The ISL6521 can employ up to 5 external transistors. Two
N-channel MOSFETs are used in the synchronous-rectified
buck topology of PWM converter. The linear controllers can
each drive an NPN bipolar transistor as a pass element. All
these transistors should be selected based upon r
current gain, saturation voltages, gate/base supply
requirements, and thermal management considerations.
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are dissipated by the ISL6521 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, t
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V) logic-
level or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6521.
P
P
UPPER
LOWER
=
=
I
----------------------------------------------------------- -
I
-------------------------------------------------------------------------------- -
O
O
2
2
×
×
SW
r
r
DS ON
DS ON
which increases the upper MOSFET
V
(
GS(ON)
(
IN
)
V
)
×
×
IN
V
(
V
OUT
characteristics, as the low gate
11
IN
–
+
V
I
----------------------------------------------------
OUT
O
×
V
)
IN
×
2
t
SW
×
F
DS(ON)
S
,
ISL6521
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, providing the body diode
is fast enough to avoid excessive negative voltage swings at
the PHASE pin. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
Linear Controller Transistor Selection
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.
If bipolar NPN transistors have to be used with the linear
controllers, insure the current gain at the given operating
V
output load current when the base is fed with the minimum
driver output current.
P
+5V
CE
LINEAR
ISL6521
is sufficiently large to provide the desired maximum
-
+
VCC
=
I
O
VCC
×
FIGURE 8. MOSFET GATE BIAS
BOOT
(
V
GND
IN
UGATE
PHASE
LGATE
PGND
–
V
C
OUT
BOOT
)
Q1
Q2
+5V OR LESS
+
CR1
V
NOTE:
V
NOTE:
GS
GS
≈
≈
V
V
CC
CC
-0.5V