ISL6326BIRZ-T Intersil, ISL6326BIRZ-T Datasheet - Page 24

• Manufacturer Part Number: ISL6326BIRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326BIRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. Record the output voltage as V1 immediately after the
11. If the output voltage increases over 2mV as the
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated
temperature compensation function is disabled. And one
external temperature compensation network, shown in
Figure 15, can be used to cancel the temperature impact on
the droop (i.e., load line).
The sensed current will flow out of the FB pin and develop a
droop voltage across the resistor equivalent (R
the FB and VDIFF pins. If R
temperature increases, the temperature impact on the droop
can be compensated. An NTC resistor can be placed close
to the power stage and used to form R
non-linear temperature characteristics of the NTC, a resistor
network is needed to make the equivalent resistance
between the FB and VDIFF pins reverse proportional to the
temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it
has no impact to the sensed current inside ISL6326B.
Therefore, this network cannot compensate for the
temperature impact on the overcurrent protection function.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
FIGURE 15. EXTERNAL TEMPERATURE COMPENSATION
output voltage is stable with the full load. Record the
output voltage as V2 after the VR reaches the thermal
steady state.
temperature increases, i.e. V2-V1 > 2mV, reduce N and
redesign R
as the temperature increases, i.e. V1-V2 > 2mV, increase
N and redesign R
TC2
o
C
; if the output voltage decreases over 2mV
TC2
COMP
.
VDIFF
FB
FB
24
resistance reduces as the
ISL6326B
Internal
circuit
FB
. Due to the
ISEN
FB
) between
ISL6326B
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (R
continuous output current; I
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
Upper MOSFET Power Calculation
In addition to R
MOSFET losses are due to currents conducted across the
input voltage (V
P
P
LOW,2
LOW 1
LOW 2
,
,
.
=
=
r
V
S
DS ON
D ON
; and the length of dead times, t
DS(ON)
(
(
DS(ON)
IN
)
) during switching. Since a substantially
)
f
S
⎛
⎜
⎝
). In Equation 24, I
I
----- -
N
M
⎛
⎝
I
----- -
⎞
⎟
⎠
N
M
losses, a large portion of the upper-
2
(
+
M
1 d
I
-------- -
, V
PP
–
PP
2
D(ON)
⎞ t
⎠
)
is the peak-to-peak inductor
+
d1
I
--------------------------------
L PP
,
+
2
; the switching
⎛
⎜
⎝
12
I
----- -
(
N
M
M
1 d
–
–
is the maximum
I
-------- -
PP
2
)
d1
⎞
⎟
⎠
OUT
t
d2
and t
LOW,1
/V
April 21, 2006
IN
d2
(EQ. 24)
(EQ. 25)
FN9286.0
); and
, at
and