ISL6327IRZ-T Intersil, ISL6327IRZ-T Datasheet
ISL6327IRZ-T
Specifications of ISL6327IRZ-T
Available stocks
Related parts for ISL6327IRZ-T
ISL6327IRZ-T Summary of contents
Page 1
... PART (Note) MARKING ISL6327CRZ* ISL6327CRZ ISL6327IRZ* ISL6327IRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
Page 2
Pinout VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL OFS IOUT DAC 2 ISL6327 ISL6327 (48 LD QFN) TOP VIEW GND 7 8 ...
Page 3
ISL6327 Block Diagram VDIFF VR_RDY RGND X1 VSEN OVP SOFT-START +175MV FAULT LOGIC SS OFS OFFSET REF DAC VRSEL VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 COMP FB 2V OC2 IOUT IDROOP 3 ISL6327 OVP OVP ...
Page 4
Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP NTC2 EXTERNAL TCOMP COMPENSATION NETWORK FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6327 VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ...
Page 5
Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6327 VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 VID0 ...
Page 6
... Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature (ISL6327CRZ 0°C to +70°C Ambient Temperature (ISL6327IRZ .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ...
Page 7
Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) PARAMETER DAC Sink Current REF Source Current REF Sink Current PIN-ADJUSTABLE OFFSET Voltage at OFS Pin OSCILLATORS Accuracy of Switching Frequency Setting Adjustment Range of Switching Frequency (Note 4) ...
Page 8
Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued) PARAMETER Leakage Current of VR_FAN VR_FAN Low Voltage VR READY AND PROTECTION MONITORS Leakage Current of VR_RDY VR_RDY Low Voltage Undervoltage Threshold VR_RDY Reset Voltage Overvoltage Protection Threshold Overvoltage ...
Page 9
... PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3, PWM4, PWM5, and PWM6. For 2-phase operation, connect PWM3 to VCC; similarly, PWM4 for 3-phase, PWM5 for 4-phase, and PWM6 for 5-phase operation ...
Page 10
Operation Multiphase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable, ...
Page 11
... Figure 22 shows the single phase input-capacitor RMS current for comparison. PWM Modulation Scheme The ISL6327 adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve the transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to provide the best response to the transient loads ...
Page 12
... Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the (EQ. 6) PWM duty cycle of each channel with Intersil’s patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area ...
Page 13
... The output of the error amplifier, V COMP sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitries, which control the voltage regulation, are illustrated in Figure 5. ...
Page 14
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 400mV 200mV 100mV 50mV 25mV 12.5mV ...
Page 15
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 400mV 200mV 100mV 50mV 25mV 12.5mV ...
Page 16
TABLE 3. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
Page 17
TABLE 3. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
Page 18
... ICs reach their POR level before the ISL6327 OFS becomes enabled. The schematic in Figure 7 ISL6327 demonstrates sequencing the ISL6327 with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR. POR ...
Page 19
Soft-Start ISL6327 based VR has 4 periods during soft-start as shown in Figure 8. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, The controller will have fixed delay period t . After this delay period, the VR will begin ...
Page 20
... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the VDIFF voltage falls below the DAC plus 75mV, PWM signals enter a high-impedance state ...
Page 21
Thermal Monitoring (VR_HOT/VR_FAN) There are two thermal signals to indicate the temperature status of the voltage regulator: VR_HOT and VR_FAN. Both VR_FAN and VR_HOT are open-drain outputs, and external pull-up resistors are required. Those signals are valid only after the ...
Page 22
In order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. ISL6327 provides two methods: integrated temperature compensation and external temperature compensation. Integrated Temperature Compensation When TCOMP voltage ...
Page 23
... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
Page 24
In Equation 26, the required time for this commutation is t approximated associated power loss is P ⎛ ⎞ ⎞ t ⎛ 1 ≈ ⎜ ⎟ ...
Page 25
R ∑ ---------- R ISEN where R is the current sensing resistor connected to ISEN(n) th the n ISEN+ pin. Compensation The two opposing goals of compensating the voltage regulator ...
Page 26
COMP IDROOP VDIFF FIGURE 18. COMPENSATION CIRCUIT FOR ISL6327 BASED CONVERTER WITHOUT LOAD-LINE REGULATION The first step is to choose the desired bandwidth, f compensated system. Choose ...
Page 27
V V – ⎝ ⎠ IN OUT OUT ( ) ≥ L ESR ----------------------------------------------------------- - MAX – transient, the capacitor voltage becomes slightly depleted. The output inductors ...
Page 28
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
Page 29
Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 29 ...