ISL6564AIRZ Intersil, ISL6564AIRZ Datasheet - Page 12

• Manufacturer Part Number: ISL6564AIRZ
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6564AIRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 21, 22 and 23 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 24 shows the single
phase input-capacitor RMS current for comparison.
I
C PP
,
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
=
(
----------------------------------------------------------- -
V
INPUT-CAPACITOR CURRENT, 10A/DIV
IN
–
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
N V
L f
CHANNEL 1
INPUT CURRENT
10A/DIV
S
OUT
V
IN
CHANNEL 2
INPUT CURRENT
10A/DIV
) V
OUT
CHANNEL 3
INPUT CURRENT
10A/DIV
12
1µs/DIV
(EQ. 2)
ISL6564A
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6564A is four. One switching cycle is defined as the time
between PWM1 pulse termination signals. The pulse
termination signal is an internally generated clock signal
which triggers the falling edge of PWM1. The cycle time of
the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
the channel 1 PWM output to go low. The PWM1 transition
signals the channel-1 MOSFET driver to turn off the
channel 1 upper MOSFET and turn on the channel 1
synchronous MOSFET. In the default channel configuration,
the PWM2 pulse terminates 1/4 of a cycle after PWM1. The
PWM3 output follows another 1/4 of a cycle after PWM2.
PWM4 terminates another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments. Connecting both PWM3 and PWM4 to VCC
selects single-channel operation.
Once a PWM signal transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
sawtooth ramp as illustrated in Figure 7. When the modified
V
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sampling
During the forced off-time following a PWM transition low,
the associated channel current sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I
sense current, I
inductor current. Coincident with the falling edge of the PWM
signal, the sample and hold circuitry samples I
illustrated in Figure 3. The sample window hold time, t
is fixed and equal to 1/3 of the switching period, t
Therefore, the sample current, I
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
overcurrent protection.
t
HOLD
COMP
COMP
, minus the current correction signal relative to the
=
voltage crosses the sawtooth ramp, the PWM output
t
--------- -
SW
3
=
SEN
----------------- -
3 f
L
⋅
. No matter the current sense method, the
1
SW
, is simply a scaled version of the
n
, is proportional to the
SEN
SW
March 20, 2007
, as
.
HOLD
(EQ. 3)
FN6285.1
,