ISL6402AIR Intersil, ISL6402AIR Datasheet - Page 14

• Manufacturer Part Number: ISL6402AIR
• Description: IC PWM BUCK CM 28QFN
• Manufacturer: Intersil

Specifications of ISL6402AIR

• Pwm Type: Current Mode
• Number Of Outputs: 3
• Frequency - Max: 1.5MHz
• Duty Cycle: 73%
• Voltage - Supply: 4.5 V ~ 24 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Due to the current loop feedback, the modulator has a single
pole response with -20
by the load.
where R
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 19 shows a Type 2 amplifier and it’s response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 10kHz to 50kHz range gives
some additional phase ‘boost’. Some phase boost can also
F
F
F
PO
Z
P
MODULATOR
G
=
=
M
=
------------------------------ -
2π R
=15.5dB
------------------------------ -
2π R
FIGURE 19. FEEDBACK LOOP COMPENSATION
-------------------------------- - ,
2π R
O
⋅
⋅
EA
⋅
1
is load resistance and C
1
F
2
1
CONVERTER
PO
1
⋅
⋅
O
C
C
⋅
1
2
C
O
=
=
10kHz
600kHz
dB
slope at a frequency determined
F
14
Z
R1
O
F
C
is load capacitance. For
G
EA
TYPE 2 EA
R2
=13dB
C2
C1
F
P
ISL6402A
be achieved by connecting capacitor C
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the output inductor and capacitor
selection sections for further details.
Linear Regulator
The linear regulator controller is a transconductance
amplifier with a nominal gain of 2 A/V. The N-channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With zero volts differential at its
input, the controller sinks 21mA of current. An external PNP
transistor or PFET pass element can be used. The dominant
pole for the loop can be placed at the base of the PNP (or
gate of the PFET), as a capacitor from emitter to base
(source to gate of a PFET). Better load transient response is
achieved however, if the dominant pole is placed at the
output, with a capacitor to ground at the output of the
regulator.
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
charge may build up on the output capacitor making V
rise above its set point. Care must be taken to insure that the
feedback resistor’s current exceeds the pass transistor’s
leakage current over the entire temperature range.
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear will track the PWM supply after the PWM output rises
to a voltage greater than the threshold of the PFET pass
device. The voltage differential between the PWM and the
linear output will be the load current times the r
Figure 20 shows the linear regulator (2.5V) startup waveform
and the PWM (3.3V) startup waveform.
FIGURE 20. LINEAR REGULATOR STARTUP WAVEFORM
Z
in parallel with the
V
V
OUT2
DS(ON)
OUT3
1V/DIV
1V/DIV
FN9010.3
LDO
.