ISL6561CRZ-T Intersil, ISL6561CRZ-T Datasheet
ISL6561CRZ-T
Specifications of ISL6561CRZ-T
Available stocks
Related parts for ISL6561CRZ-T
ISL6561CRZ-T Summary of contents
Page 1
... PCB Efficiency, Thinner in Profile CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 Dynamic VID™ trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6561 May 12, 2005 FN9098 ...
Page 2
... PART NUMBER (°C) PACKAGE ISL6561CR 6x6 QFN ISL6561CR 6x6 QFN Tape and Reel ISL6561CRZ (Note 6x6 QFN (Pb-free) L40.6x6 ISL6561CRZ-T (Note 6x6 QFN Tape and Reel (Pb-free) ISL6561CRZA (Note 6x6 QFN (Pb-free) L40.6x6 ISL6561CRZA 6x6 QFN Tape and Reel (Note) (Pb-free) ISL6561IR ...
Page 3
ISL6561CR Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB IDROOP TCOMP T 3 ISL6561 OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q ...
Page 4
Typical Application - 4-Phase Buck Converter with Rds,on Sensing and External NTC FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND VIDPGOOD ENLL PGOOD ISL6561 OVP ISEN1+ VID4 ISEN1- VID3 PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ...
Page 5
Typical Application - 4-Phase Buck Converter with r FB REF COMP IDROOP DAC VDIFF VSEN VCC RGND VIDPGOOD ENLL ISL6561 PGOOD OVP ISEN1+ VID4 ISEN1- VID3 PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- OFS PWM4 FS ...
Page 6
Typical Application - 4-Phase Buck Converter with DCR Sensing and External NTC FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND VIDPGOOD ENLL PGOOD ISL6561 OVP ISEN1+ VID4 ISEN1- VID3 PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ...
Page 7
Typical Application - 4-Phase Buck Converter with DCR Sensing and Internal PTC FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND VIDPGOOD ENLL ISL6561 PGOOD OVP ISEN1+ VID4 ISEN1- VID3 PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ...
Page 8
... Operating Conditions Supply Voltage, VCC (5V bias mode, Note +5V ±5% Ambient Temperature (ISL6561CR, ISL6561CRZ 0°C to 70°C Ambient Temperature (ISL6561IR, ISL6561IRZ -40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
Page 9
Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS pin OSCILLATOR Accuracy Adjustment Range Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew ...
Page 10
... VID™ operations. PWM1, PWM2, PWM3, PWM4 - Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. ...
Page 11
OVP - Overvoltage protection pin. This pin pulls to VCC and is latched when an overvoltage condition is detected. Connect this pin to the gate of an SCR or MOSFET tied from ground to prevent damage ...
Page 12
Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors – IN OUT OUT I = ----------------------------------------------------------- - Another ...
Page 13
... Intersil’s patented current-balance method is illustrated in Figure 6, with error correction for channel 1 represented. In the figure, the cycle average current ...
Page 14
... The output of the error amplifier, V COMP sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry that controls voltage regulation is illustrated in Figure 7. ...
Page 15
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued) VID4 VID3 VID2 VID1 VID0 ...
Page 16
DAC and REF selected so that the product REF ( equal to the desired offset voltage. These OFS REF functions are shown in Figures 8. FB DYNAMIC VID D/A E/A - 2.0V ...
Page 17
... It is important that the driver ICs reach their POR level before the ISL6561 becomes enabled. The schematic in Figure 9 demonstrates sequencing the ISL6561 with the HIP660X family of Intersil MOSFET drivers, which require 12V bias The voltage on ENLL must be logic high to enable the controller ...
Page 18
... VSEN falls below 0.6V with valid VCC or 1.5V otherwise. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The PWM outputs remain low until VDIFF falls to the programmed DAC level when they enter a high-impedance state ...
Page 19
... At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft start ...
Page 20
LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance ( Equation 15, ...
Page 21
In Equation 22, make sure that ∆T is the desired temperature 2 rise above the ambient temperature, and ∆T temperature rise above the ambient temperature. While a single adjustment according to Equation 22 is usually sufficient, it may occasionally be ...
Page 22
COMP IDROOP VDIFF FIGURE 14. COMPENSATION CIRCUIT FOR ISL6561 BASED CONVERTER WITHOUT LOAD-LINE REGULATION The optional capacitor sometimes needed to bypass 2 noise away ...
Page 23
Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount di ∆V ≈ ∆I ESL ---- - + ESR dt The ...
Page 24
L, 0 0. 0.2 0.4 0.6 DUTY CYCLE (V O FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 2-PHASE CONVERTER ...
Page 25
... Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals ...
Page 26
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...