ISL6217ACVZ-T Intersil, ISL6217ACVZ-T Datasheet - Page 16

• Manufacturer Part Number: ISL6217ACVZ-T
• Description: IC CTRLR PWM INTEL PENT 38-TSSOP
• Manufacturer: Intersil

Specifications of ISL6217ACVZ-T

• Applications: Controller, Intel Pentium® IMVP-IV, IMVP+
• Voltage - Input: 5.5 ~ 25 V
• Number Of Outputs: 1
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Voltage Loop
The output CORE voltage feedback is applied to the Error
Amplifier through the compensation network. The signal
seen on the FB pin will drive the Error Amplifier output either
high or low, depending on the CORE voltage. A CORE
voltage level that is lower than the IMVP-IV™ and
IMVP-IV+™ reference, as output from the 6 bit DAC, makes
the amplifier output move towards a higher output voltage
level. The amplifier output voltage is applied to the positive
inputs of the comparators by the BALANCE summing
networks. Out-of-phase sawtooth signals are applied to the
two comparator inverting inputs. Increasing Error Amplifier
voltage results in increased Comparator output duty cycle.
This increased duty cycle signal is passed through the PWM
circuit to the internal gate-drive circuitry. The output of the
internal gate-drive is directly connected to the gate of the
MOSFETs. Increased duty cycle or ON-time for the high side
MOSFET transistors results in increased output voltage,
VCORE, to compensate for the low output voltage sensed.
Current Loop
The current control loop keeps the channel currents in
balance. During the PWM off-time of each channel, the
voltage Vr DS(ON) , developed across the lower MOSFET is
sampled. Internally, the ISEN pin is held at virtual ground
during this interval, and Vr
R ISEN resistor. This provides current feedback proportional
to the output current of each channel. The scaled output
currents from all active channels are combined to create an
average current reference I AVERAGE , proportional to the
converter total output current. This signal is then subtracted
from the individual channel scaled output currents to
produce a current correction signal for each channel. The
current correction signal keeps each channel output current
contribution balanced relative to the other active channels.
Each current correction signal is subtracted from the error
amplifier output and fed to the individual channel PWM
circuits. For example, assume the voltage sampled across
Q4 in Figure 9 is higher than that sampled across Q2. The
ISEN2 current would be higher than ISEN1. When the two
reference currents are averaged, they accurately represent
the total output current of the converter. The reference
current I AVERAGE is then subtracted from the ISEN
currents. This results in a positive offset for Channel 2 and a
negative offset for Channel 1. These offsets are subtracted
from the error amplifier signal and perform phase balance
correction. The V ERROR2 signal is reduced, while
V ERROR1 would be increased. The PWM circuit would then
reduce the pulse width to lower the output current
contribution by Channel 2, while doing the opposite to
Channel 1, thereby balancing channel currents.
Droop Compensation
Microprocessors and other peripherals tend to change their
load current demands from near no-load to full load often
DS(ON)
16
is impressed across the
ISL6217A
STATIC TOLERANCE BANDS
-3 m _
load line
V
during operation. These same devices require minimal
output voltage deviation during a load step.
A high di/dt load step will cause an output voltage spike. The
amplitude of the spike is dictated by the output capacitor
ESR, multiplied by the load step magnitude, plus the output
capacitor ESL, times the load step di/dt. A positive load step
produces a negative output voltage spike and vice versa. A
large number of low-series-impedance capacitors are often
used to prevent the output voltage deviation from exceeding
the tolerance of some devices. One widely accepted solution
to this problem is output voltage “Droop”, or active voltage
positioning.
As shown in Figure 3 and Figure 9, the average channel
current is used to control the “Droop” current source,
I DROOP . The “Droop” current source is a controlled current
source and is proportional to output current. This current
source is approximately 87% of the averaged ISEN currents.
The Droop current is sourced out of the SOFT pin through
the Droop resistor and returns through the EA+ pin. This
creates a “Droop” voltage V DROOP , which subtracts from
the IMVP- IV™ and IMVP-IV+™ reference voltage on SOFT
to generate the voltage set point for the CORE regulator.
Full load current for the Intel IMVP-IV™ and IMVP-IV+™
specification is 32A. Knowing that the Droop Current,
sourced out of the SOFT pin, will be 87% of the ISEN
averaged currents, a “Droop” resistor R DROOP , can be
selected to provide the amount of voltage “Droop” required
at full load. The selection of this resistor is explained in the
following section.
Selection of RDROOP
Figure 11 shows a static “Droop” load line for the 1.484V
Active Mode. The ISL6217A, as previously mentioned,
allows the programming of the load line slope by the
selection of the RDROOP resistor.
As per the Intel IMVP-IV™ and IMVP-IV+™ specification,
Droop = 0.003 (Ω). Therefore, 25A of full load current
equates to a 0.075V Droop output voltage from the VID
setpoint. Refer to Figure 3 and Figure 9, R
OUT,NOM
V
V
OUT,LO
OUT,HI
FIGURE 11. IMVP-IV ACTIVE MODE STATIC LOAD LINE
I
OUT,NL
(0A,1.506V)
(0A,1.484V)
I
OUT,MID
NOMINAL "DROOP" LOAD LINE
(0A,1.462V)
DROOP
I
OUT,MAX
June 30, 2005
can be
(25A,1.431V)
(25A,1.409V)
(25A,1.387V)
FN9107.3