ISL6217ACVZ-T Intersil, ISL6217ACVZ-T Datasheet
ISL6217ACVZ-T
Specifications of ISL6217ACVZ-T
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ISL6217ACVZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6217A ...
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... PACKAGE ISL6217ACV - TSSOP ISL6217ACV TSSOP Tape and Reel ISL6217ACVZ - TSSOP (Note 1) (Pb-free) ISL6217ACVZ TSSOP Tape and Reel (Note 1) (Pb-free) ISL6217ACVZA - TSSOP (Pb-free) ISL6217ACVZA TSSOP Tape and Reel (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Absolute Voltage Ratings Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7V Battery Voltage, VBAT . . . . . ...
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Electrical Specifications Operating Conditions: VDD = 5V, T PARAMETER UGATE Sink Resistance 500mA Sink Current UGATE Sink Current V UGATE-PHASE = 2.5V LGATE Source Resistance 500mA Source Current LGATE Source Current V LGATE = 2.5V LGATE Sink Resistance 500mA Sink ...
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Functional Pin Description VDD - This pin is used to connect +5V to the IC to supply all power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold ...
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Block Diagram VSEN + OVP - FAULT LOGIC 112% RISING 102% FALLING 88% RISING 84% FALLING - + UV 32 COUNT CLOCK CYCLE DACOUT V SOFT SOFT SOFT START EA+ VID0 VID1 VID2 VID VID3 D/A VID4 VID5 COMP FB ...
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Typical Application - 2-Phase Converter Figure 1 shows a 2-Phase Synchronous Buck Converter circuit used to provide “CORE” voltage regulation for the Intel Pentium IV mobile processor using IMVP-IV™ and IMVP-IV+™ voltage positioning. The ISL6217A PWM controller can be configured ...
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... The ISL6217A PGOOD pin is both an input and an output. The system signal, IMVP4_PWRGD, is connected to power good signals from the Vccp and Vcc_mch supplies. The Intersil ISL6227, Dual Voltage Regulator is an ideal choice for the Vccp and Vcc_mch supplies. Once the output voltage is within the “Boot” level regulation ...
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Active, Deep and Deeper Sleep slew rate requirements of the Intel IMVP-IV™ and IMVP-IV+™ specification. ISL6217A DROOP R EA+ SOFT DROOP + V DROOP C SOFT FIGURE 3. SOFT-START TRACKING CIRCUITRY SHOWING INTERNAL ...
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TABLE 1. IMPV-IV VID CODES VID5 VID4 VID3 VID2 VID1 ...
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Active, Deep Sleep and Deeper Sleep Modes The ISL6217A Multi-Phase Controller is designed to control the CORE output voltage as per the IMVP-IV™ and IMVP-IV+™ specifications for Active, Deep Sleep, and Deeper Sleep Modes of Operation. After initial Start-up, a ...
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A logic low signal present on STPCPU# (pin DSEN#), with a logic low signal on DPRSLPVR (pin DRSEN), signals the ISL6217A to reduce the CORE output voltage to the Deep Sleep level, the voltage on the DSV pin, and to ...
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Overcurrent Setting - OCSET The ISL6217A overcurrent protection essentially compares a user-selectable overcurrent Threshold to the scaled and sampled output current. An overcurrent condition is defined when the sampled current is equal to or greater than the threshold current. A ...
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... FIGURE 10. INTERNAL PGOOD CIRCUITRY FOR THE As per the IMVP-IV™ and IMVP-IV+™ specification, once the ISL6217A CORE regulator regulates to the “Boot” voltage, it waits for the PGOOD logic HIGH signals from the Vccp and Vcc_mch regulators. The Intersil ISL6227 UG1 ...
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PGOOD functions for each supply. Once these two supplies are within regulation, PGOOD Vccp and PGOOD Vcc_mch will be high impedance, and will allow the ...
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Voltage Loop The output CORE voltage feedback is applied to the Error Amplifier through the compensation network. The signal seen on the FB pin will drive the Error Amplifier output either high or low, depending on the CORE voltage. A ...
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R which is calculated through ISEN Equation and Droop as per the Block Diagram or DS(ON) the following equation ISEN = ⋅ ⋅ Ω Droop ( DROOP ...
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FIGURE 12. OUTPUT RIPPLE CURRENT MULTIPLIER vs DUTY CYCLE Find the intersection of the active channel curve and duty cycle for your particular application. The resulting ripple current multiplier from the y-axis is then multiplied by the normalization factor K ...
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× OUT UPPER V IN Typical Application - 2 Phase Converter Using ISL6217A PWM Controller - 38 Lead TSSOP Figure 14 shows the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...