ISL6334CCRZ-T Intersil, ISL6334CCRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL6334CCRZ-T
• Description: IC CTRLR PWM SYNC BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6334CCRZ-T

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334B,
ISL6334C is released from shutdown mode.
C
1. The bias voltage applied at VCC must reach the internal
REF
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334B, ISL6334C are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334B, ISL6334C will not inadvertently turn
off unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
⋅
FAULT LOGIC
CIRCUIT
SOFT-START
R
REF
POR
AND
SENSITIVE ENABLE (EN) FUNCTION
=
t
ISL6334B, ISL6334C
VID
COMPARATOR
ENABLE
20
+
-
0.875V
+
0.875V
-
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
100kΩ
9.1kΩ
+12V
ISL6334B, ISL6334C
(EQ. 13)
When all conditions previously mentioned are satisfied,
ISL6334B, ISL6334C begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334B, ISL6334C reads the VID code at VID input
pins. If the VID code is valid, ISL6334B, ISL6334C will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334B, ISL6334C will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6334B, ISL6334C based VR has 4 periods during soft-start,
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period t
soft-start ramp until the output voltage reaches 1.1V V
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t
ISL6334C reads the VID signals. If the VID code is valid,
ISL6334B, ISL6334C will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods, as shown in
Equation 14.
t
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
t
D1
2. The ISL6334B, ISL6334C features an enable input
3. The voltage on EN_VTT must be higher than 0.875V to
SS
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334B, ISL6334C in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334B, ISL6334C becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334B, ISL6334C with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
is a fixed delay with the typical value as 1.36ms. t
=
t
D1
+
FIGURE 9. SOFT-START WAVEFORMS
t
D2
D1
+
. After this delay period, the VR will begin first
VOUT, 500mV/DIV
t
D3
t
D1
+
t
EN_VTT
VR_RDY
D4
D3
. At the end of t
t
D2
500µs/DIV
t
D3
t
D4
D3
t
period, ISL6334B,
D5
August 31, 2010
BOOT
(EQ. 14)
D3
FN6689.2
is