ISL6264CRZ Intersil, ISL6264CRZ Datasheet - Page 18

• Manufacturer Part Number: ISL6264CRZ
• Description: IC CORE CTRLR TWO-PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6264CRZ

• Applications: Controller, AMD Mobile Turion™
• Voltage - Input: 5 ~ 24 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Using a SLEWRATE of 4.2mV/µs, and the typical I
given in the Electrical Specification table of 230µA, C
shown in Equation 3:
A choice of 0.047µF would guarantee a SLEWRATE of
3.7mV/µs is met for minimum I
Table Electrical Specifications on page 2. This choice of
C
should expect the output voltage to slew to the VID value of
1.2V at a rate given by Equation 4:
Selecting R
To properly bias the ISL6264, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10A current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the R
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-up Operation - PGOOD
The internal timer allows PGOOD to go high approximately
7.6ms after Vout reaches the target VID voltage during the
start-up.
C
dV
-------
dt
SOFT
SOFT
=
------------------ -
C
will then control the Start-Up slew rate as well. One
≡
ISEN1
OC
SOFT
I
SS
(
230μA
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
VDIFF
INTERNAL TO
ISEN1
BIAS
ISL6264
=
0.018µF
---------------------- -
0.047μF
)
S
-
+
⁄
43μA
(
4.2
+
+
ISEN2
10µA
R
)
OPN2
RTN
1
1
=
+
+
-
-
0.9
ISEN2
18
0.018µF
mV
3
DROOP
value, given in the
VSEN
⁄
(
μS
+
-
)
DROOP
OCSET
10
VSUM
DFB
VCC_SENSE
VSS_SENSE
R
VO'
OPN1
R
BIAS
OCSET
2
value,
TO V
SOFT
(EQ. 3)
(EQ. 4)
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
OUT
is
V
ISL6264
O'
VSUM
R
V
O'
OCSET
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6264 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are V
V
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode capacitor filters to analog ground on VSEN and RTN.
Whether to need these capacitors really depends on the
actual board layout and noise environment.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an over voltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to V
(illustrated in Figure 31). These resistors will provide voltage
feedback in the event that the system is powered up without
a processor installed. These resistors may typically range
from 20Ω to 100Ω.
CC_SENSE
VSUM
VSUM
I
I
PHASE1
PHASE2
respectively. This allows the voltage regulator to
RS
RS
ISEN2
ISEN1
R
R
L2
L
L1
2
L
1
+
VO'
VDCR 2
C
C
L2
L1
+
VO'
-
VDCR
DCR
DCR
RO1
-
1
RO2
OUT
CC_SENSE
and ground
ESR
V
C
May 28, 2009
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